From: Tom Rini Date: Thu, 10 Nov 2022 15:09:02 +0000 (-0500) Subject: Merge branch '2022-11-10-symbol-migrations' X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=0cbeed4f6648e0e4966475e3544280a69ecb59d3;p=u-boot.git Merge branch '2022-11-10-symbol-migrations' - Migrate a number of CONFIG symbols to Kconfig and start migrating some symbol families from CONFIG to the CFG namespace. --- 0cbeed4f6648e0e4966475e3544280a69ecb59d3 diff --cc include/configs/corenet_ds.h index 434da31444,434da31444..0000000000 deleted file mode 100644,100644 --- a/include/configs/corenet_ds.h +++ /dev/null @@@ -1,365 -1,365 +1,0 @@@ --/* SPDX-License-Identifier: GPL-2.0+ */ --/* -- * Copyright 2009-2012 Freescale Semiconductor, Inc. -- * Copyright 2020-2021 NXP -- */ -- --/* -- * Corenet DS style board configuration file -- */ --#ifndef __CONFIG_H --#define __CONFIG_H -- --#include -- --#include "../board/freescale/common/ics307_clk.h" -- --#ifdef CONFIG_RAMBOOT_PBL --#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_TEXT_BASE --#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc --#endif -- --#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE --/* Set 1M boot space */ --#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) --#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ -- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) --#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc --#endif -- --/* High Level Configuration Options */ -- --#ifndef CONFIG_RESET_VECTOR_ADDRESS --#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc --#endif -- --#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -- --/* -- * These can be toggled for performance analysis, otherwise use default. -- */ --#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E --#ifdef CONFIG_DDR_ECC --#define CONFIG_MEM_INIT_VALUE 0xdeadbeef --#endif -- --#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ -- --/* -- * Config the L3 Cache as L3 SRAM -- */ --#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE --#ifdef CONFIG_PHYS_64BIT --#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) --#else --#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR --#endif --#define CONFIG_SYS_L3_SIZE (1024 << 10) --#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) -- --#ifdef CONFIG_PHYS_64BIT --#define CONFIG_SYS_DCSRBAR 0xf0000000 --#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull --#endif -- --/* -- * DDR Setup -- */ --#define CONFIG_VERY_BIG_RAM --#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 --#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -- --#define SPD_EEPROM_ADDRESS1 0x51 --#define SPD_EEPROM_ADDRESS2 0x52 --#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ --#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ -- --/* -- * Local Bus Definitions -- */ -- --/* Set the local bus clock 1/8 of platform clock */ --#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 -- --#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ --#ifdef CONFIG_PHYS_64BIT --#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull --#else --#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE --#endif -- --#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ --#ifdef CONFIG_PHYS_64BIT --#define PIXIS_BASE_PHYS 0xfffdf0000ull --#else --#define PIXIS_BASE_PHYS PIXIS_BASE --#endif -- --#define PIXIS_LBMAP_SWITCH 7 --#define PIXIS_LBMAP_MASK 0xf0 --#define PIXIS_LBMAP_SHIFT 4 --#define PIXIS_LBMAP_ALTBANK 0x40 -- --#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -- --/* Nand Flash */ --#ifdef CONFIG_NAND_FSL_ELBC --#define CONFIG_SYS_NAND_BASE 0xffa00000 --#ifdef CONFIG_PHYS_64BIT --#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull --#else --#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE --#endif -- --#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} --#define CONFIG_SYS_MAX_NAND_DEVICE 1 -- --/* NAND flash config */ --#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ -- | (2<> 1) --#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ -- CONFIG_SYS_BMAN_CENA_SIZE) --#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) --#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 --#define CONFIG_SYS_QMAN_NUM_PORTALS 10 --#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 --#ifdef CONFIG_PHYS_64BIT --#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull --#else --#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE --#endif --#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 --#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 --#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 --#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE --#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) --#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ -- CONFIG_SYS_QMAN_CENA_SIZE) --#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) --#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 -- --#define CONFIG_SYS_DPAA_FMAN --#define CONFIG_SYS_DPAA_PME -- --#ifdef CONFIG_FMAN_ENET --#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c --#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d --#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e --#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f --#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 -- --#define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c --#define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d --#define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e --#define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f --#define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 -- --#define CONFIG_SYS_TBIPA_VALUE 8 --#endif -- --/* -- * Environment -- */ --#define CONFIG_LOADS_ECHO /* echo on for serial download */ --#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ -- --#ifdef CONFIG_MMC --#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR --#endif -- --/* -- * Miscellaneous configurable options -- */ -- --/* -- * For booting Linux, the board info and command line data -- * have to be in the first 64 MB of memory, since this is -- * the maximum mapped by the Linux kernel during initialization. -- */ --#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -- --/* -- * Environment Configuration -- */ --#define CONFIG_ROOTPATH "/opt/nfsroot" --#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ -- --#ifdef CONFIG_TARGET_P4080DS --#define __USB_PHY_TYPE ulpi --#else --#define __USB_PHY_TYPE utmi --#endif -- --#define CONFIG_EXTRA_ENV_SETTINGS \ -- "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ -- "bank_intlv=cs0_cs1;" \ -- "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ -- "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ -- "netdev=eth0\0" \ -- "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ -- "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \ -- "tftpflash=tftpboot $loadaddr $uboot && " \ -- "protect off $ubootaddr +$filesize && " \ -- "erase $ubootaddr +$filesize && " \ -- "cp.b $loadaddr $ubootaddr $filesize && " \ -- "protect on $ubootaddr +$filesize && " \ -- "cmp.b $loadaddr $ubootaddr $filesize\0" \ -- "consoledev=ttyS0\0" \ -- "ramdiskaddr=2000000\0" \ -- "ramdiskfile=p4080ds/ramdisk.uboot\0" \ -- "fdtaddr=1e00000\0" \ -- "fdtfile=p4080ds/p4080ds.dtb\0" \ -- "bdev=sda3\0" -- --#include -- --#endif /* __CONFIG_H */ diff --cc scripts/config_whitelist.txt index c3e0f532f7,c3e0f532f7..c0f55e41a5 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@@ -66,148 -66,148 +66,6 @@@ CONFIG_G_DNL_UMS_VENDOR_NU CONFIG_HDMI_ENCODER_I2C_ADDR CONFIG_HIKEY_GPIO CONFIG_HOSTNAME --CONFIG_HPS_ALTERAGRP_DBGATCLK --CONFIG_HPS_ALTERAGRP_MAINCLK --CONFIG_HPS_ALTERAGRP_MPUCLK --CONFIG_HPS_CLK_CAN0_HZ --CONFIG_HPS_CLK_CAN1_HZ --CONFIG_HPS_CLK_EMAC0_HZ --CONFIG_HPS_CLK_EMAC1_HZ --CONFIG_HPS_CLK_F2S_PER_REF_HZ --CONFIG_HPS_CLK_F2S_SDR_REF_HZ --CONFIG_HPS_CLK_GPIODB_HZ --CONFIG_HPS_CLK_L4_MP_HZ --CONFIG_HPS_CLK_L4_SP_HZ --CONFIG_HPS_CLK_MAINVCO_HZ --CONFIG_HPS_CLK_NAND_HZ --CONFIG_HPS_CLK_OSC1_HZ --CONFIG_HPS_CLK_OSC2_HZ --CONFIG_HPS_CLK_PERVCO_HZ --CONFIG_HPS_CLK_QSPI_HZ --CONFIG_HPS_CLK_SDMMC_HZ --CONFIG_HPS_CLK_SDRVCO_HZ --CONFIG_HPS_CLK_SPIM_HZ --CONFIG_HPS_CLK_USBCLK_HZ --CONFIG_HPS_DBCTRL_STAYOSC1 --CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH --CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH --CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH --CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH --CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT --CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT --CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK --CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK --CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP --CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP --CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT --CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK --CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK --CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK --CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK --CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT --CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT --CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT --CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK --CONFIG_HPS_MAINPLLGRP_VCO_DENOM --CONFIG_HPS_MAINPLLGRP_VCO_NUMER --CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK --CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK --CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK --CONFIG_HPS_PERPLLGRP_DIV_USBCLK --CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT --CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT --CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK --CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT --CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT --CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT --CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT --CONFIG_HPS_PERPLLGRP_SRC_NAND --CONFIG_HPS_PERPLLGRP_SRC_QSPI --CONFIG_HPS_PERPLLGRP_SRC_SDMMC --CONFIG_HPS_PERPLLGRP_VCO_DENOM --CONFIG_HPS_PERPLLGRP_VCO_NUMER --CONFIG_HPS_PERPLLGRP_VCO_PSRC --CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT --CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE --CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT --CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE --CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT --CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE --CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT --CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE --CONFIG_HPS_SDRPLLGRP_VCO_DENOM --CONFIG_HPS_SDRPLLGRP_VCO_NUMER --CONFIG_HPS_SDRPLLGRP_VCO_SSRC --CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR --CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP --CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH --CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP --CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER --CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN --CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN --CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN --CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL --CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE --CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS --CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN --CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT --CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH --CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS --CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS --CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS --CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS --CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH --CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH --CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN --CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ --CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE --CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL --CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL --CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL --CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW --CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC --CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD --CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD --CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI --CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP --CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR --CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR --CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD --CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD --CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS --CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC --CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP --CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT --CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT --CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC --CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE --CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST --CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED --CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED --CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED --CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK --CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES --CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES --CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 --CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 --CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 --CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 --CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 --CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY --CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 --CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 --CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 --CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 --CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 --CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 --CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 --CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 --CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 --CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN --CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP --CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL --CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA --CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP CONFIG_HSMMC2_8BIT CONFIG_HWCONFIG CONFIG_HW_ENV_SETTINGS @@@ -262,7 -262,7 +120,6 @@@ CONFIG_KSNET_SERDES_SGMII_BAS CONFIG_L1_INIT_RAM CONFIG_L2_CACHE CONFIG_LEGACY_BOOTCMD_ENV --CONFIG_LOADS_ECHO CONFIG_LOWPOWER_ADDR CONFIG_LOWPOWER_FLAG CONFIG_LPC32XX_HSUART @@@ -382,7 -382,7 +239,6 @@@ CONFIG_RTC_DS133 CONFIG_RTC_DS1374 CONFIG_RTC_DS3231 CONFIG_RTC_MC13XXX --CONFIG_RTC_MCFRRTC CONFIG_RTC_MXS CONFIG_RTC_PT7C4338 CONFIG_SANDBOX_ARCH @@@ -661,111 -661,111 +517,6 @@@ CONFIG_SYS_FPGA_FTIM CONFIG_SYS_FPGA_FTIM3 CONFIG_SYS_FPGA_SIZE CONFIG_SYS_FPGA_WAIT --CONFIG_SYS_FSL_BMAN_ADDR --CONFIG_SYS_FSL_BMAN_OFFSET --CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR --CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR --CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR --CONFIG_SYS_FSL_CLK_ADDR --CONFIG_SYS_FSL_CLUSTER_1_L2 --CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET --CONFIG_SYS_FSL_CLUSTER_CLOCKS --CONFIG_SYS_FSL_CORENET_CCM_ADDR --CONFIG_SYS_FSL_CORENET_CCM_OFFSET --CONFIG_SYS_FSL_CORENET_CLK_ADDR --CONFIG_SYS_FSL_CORENET_CLK_OFFSET --CONFIG_SYS_FSL_CORENET_PMAN --CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET --CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET --CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET --CONFIG_SYS_FSL_CORENET_PME_ADDR --CONFIG_SYS_FSL_CORENET_PME_OFFSET --CONFIG_SYS_FSL_CORENET_RCPM_ADDR --CONFIG_SYS_FSL_CORENET_RCPM_OFFSET --CONFIG_SYS_FSL_CORENET_RMAN_ADDR --CONFIG_SYS_FSL_CORENET_RMAN_OFFSET --CONFIG_SYS_FSL_CORENET_SERDES2_ADDR --CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET --CONFIG_SYS_FSL_CORENET_SERDES3_ADDR --CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET --CONFIG_SYS_FSL_CORENET_SERDES4_ADDR --CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET --CONFIG_SYS_FSL_CORENET_SERDES_ADDR --CONFIG_SYS_FSL_CORENET_SERDES_OFFSET --CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY --CONFIG_SYS_FSL_CPC_ADDR --CONFIG_SYS_FSL_CPC_OFFSET --CONFIG_SYS_FSL_CSU_ADDR --CONFIG_SYS_FSL_DCSR_DDR2_ADDR --CONFIG_SYS_FSL_DCSR_DDR3_ADDR --CONFIG_SYS_FSL_DCSR_DDR_ADDR --CONFIG_SYS_FSL_DDR2_ADDR --CONFIG_SYS_FSL_DDR3_ADDR --CONFIG_SYS_FSL_DDR_ADDR --CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY --CONFIG_SYS_FSL_ESDHC_ADDR --CONFIG_SYS_FSL_FM --CONFIG_SYS_FSL_FM1_ADDR --CONFIG_SYS_FSL_FM1_DTSEC1_ADDR --CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET --CONFIG_SYS_FSL_FM1_OFFSET --CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET --CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET --CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET --CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET --CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET --CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET --CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET --CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET --CONFIG_SYS_FSL_FM2_ADDR --CONFIG_SYS_FSL_FM2_OFFSET --CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET --CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET --CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET --CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET --CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET --CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET --CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET --CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET --CONFIG_SYS_FSL_GUTS_ADDR --CONFIG_SYS_FSL_JR0_ADDR --CONFIG_SYS_FSL_JR0_OFFSET --CONFIG_SYS_FSL_LS1_CLK_ADDR --CONFIG_SYS_FSL_LSCH3_SERDES_ADDR --CONFIG_SYS_FSL_NUM_CC_PLL --CONFIG_SYS_FSL_OCRAM_BASE --CONFIG_SYS_FSL_OCRAM_SIZE --CONFIG_SYS_FSL_PAMU_OFFSET --CONFIG_SYS_FSL_PMIC_I2C_ADDR --CONFIG_SYS_FSL_PMU_ADDR --CONFIG_SYS_FSL_PMU_CLTBENR --CONFIG_SYS_FSL_QMAN_ADDR --CONFIG_SYS_FSL_QMAN_OFFSET --CONFIG_SYS_FSL_QSPI_BASE --CONFIG_SYS_FSL_RAID_ENGINE_ADDR --CONFIG_SYS_FSL_RAID_ENGINE_OFFSET --CONFIG_SYS_FSL_RCPM_ADDR --CONFIG_SYS_FSL_RST_ADDR --CONFIG_SYS_FSL_SCFG_ADDR --CONFIG_SYS_FSL_SCFG_OFFSET --CONFIG_SYS_FSL_SEC_ADDR --CONFIG_SYS_FSL_SEC_IDX_OFFSET --CONFIG_SYS_FSL_SEC_OFFSET --CONFIG_SYS_FSL_SERDES --CONFIG_SYS_FSL_SERDES_ADDR --CONFIG_SYS_FSL_SRDS_3 --CONFIG_SYS_FSL_SRDS_4 --CONFIG_SYS_FSL_SRIO_ADDR --CONFIG_SYS_FSL_SRIO_IB_WIN_NUM --CONFIG_SYS_FSL_SRIO_MAX_PORTS --CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM --CONFIG_SYS_FSL_SRIO_OB_WIN_NUM --CONFIG_SYS_FSL_SRIO_OFFSET --CONFIG_SYS_FSL_TIMER_ADDR --CONFIG_SYS_FSL_USDHC_NUM --CONFIG_SYS_FSL_WRIOP1_ADDR --CONFIG_SYS_FSL_WRIOP1_MDIO1 --CONFIG_SYS_FSL_WRIOP1_MDIO2 CONFIG_SYS_GPIO1_EN CONFIG_SYS_GPIO1_FUNC CONFIG_SYS_GPIO1_LED @@@ -780,7 -780,7 +531,6 @@@ CONFIG_SYS_I2C_EXPANDER_ADD CONFIG_SYS_I2C_FPGA_ADDR CONFIG_SYS_I2C_G762_ADDR CONFIG_SYS_I2C_IFDR_DIV --CONFIG_SYS_I2C_INIT_BOARD CONFIG_SYS_I2C_MAX_HOPS CONFIG_SYS_I2C_NOPROBES CONFIG_SYS_I2C_PCA953X_ADDR @@@ -802,32 -802,32 +552,21 @@@ CONFIG_SYS_INIT_L2_ADDR_PHY CONFIG_SYS_INIT_L2_END CONFIG_SYS_INIT_L3_ADDR CONFIG_SYS_INIT_L3_ADDR_PHYS --CONFIG_SYS_INIT_L3_END CONFIG_SYS_INIT_L3_VADDR CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_CTRL --CONFIG_SYS_INIT_RAM_LOCK CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_INIT_SP_OFFSET --CONFIG_SYS_INTERLAKEN CONFIG_SYS_INT_FLASH_BASE CONFIG_SYS_INT_FLASH_ENABLE CONFIG_SYS_IO_BASE --CONFIG_SYS_ISA_IO --CONFIG_SYS_ISA_IO_BASE_ADDRESS --CONFIG_SYS_JFFS2_FIRST_BANK --CONFIG_SYS_JFFS2_FIRST_SECTOR --CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_KMBEC_FPGA_BASE CONFIG_SYS_KMBEC_FPGA_SIZE --CONFIG_SYS_L2_SIZE --CONFIG_SYS_L3_SIZE CONFIG_SYS_LATCH_ADDR CONFIG_SYS_LBC_ADDR --CONFIG_SYS_LBC_CACHE_BASE CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_LBC_LBCR CONFIG_SYS_LBC_LCRR @@@ -839,8 -839,8 +578,6 @@@ CONFIG_SYS_LBC_SDRAM_BASE_PHY CONFIG_SYS_LBC_SDRAM_SIZE CONFIG_SYS_LDB_CLOCK CONFIG_SYS_LIME_BASE --CONFIG_SYS_LIME_SIZE --CONFIG_SYS_LOADS_BAUD_CHANGE CONFIG_SYS_LOW CONFIG_SYS_LOWMEM_BASE CONFIG_SYS_LPAE_SDRAM_BASE @@@ -852,18 -852,18 +589,14 @@@ CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSE CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET --CONFIG_SYS_M41T11_BASE_YEAR CONFIG_SYS_MAIN_PWR_ON --CONFIG_SYS_MAMR CONFIG_SYS_MASTER_CLOCK CONFIG_SYS_MATRIX_EBI0CSA_VAL CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MAX_I2C_BUS CONFIG_SYS_MAX_NAND_CHIPS --CONFIG_SYS_MAX_NAND_DEVICE CONFIG_SYS_MBAR CONFIG_SYS_MBAR2 --CONFIG_SYS_MCFRRTC_BASE CONFIG_SYS_MCKR CONFIG_SYS_MCKR1_VAL CONFIG_SYS_MCKR2_VAL @@@ -874,79 -874,79 +607,12 @@@ CONFIG_SYS_MEM_RESERVE_SECUR CONFIG_SYS_MFD CONFIG_SYS_MMC_CD_PIN CONFIG_SYS_MMC_CLK_OD --CONFIG_SYS_MMC_MAX_BLK_COUNT --CONFIG_SYS_MMC_MAX_DEVICE CONFIG_SYS_MMC_U_BOOT_DST CONFIG_SYS_MMC_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_SIZE CONFIG_SYS_MMC_U_BOOT_START --CONFIG_SYS_MONITOR_LEN --CONFIG_SYS_MONITOR_SEC CONFIG_SYS_MOR_VAL --CONFIG_SYS_MPC83xx_DMA_ADDR --CONFIG_SYS_MPC83xx_DMA_OFFSET --CONFIG_SYS_MPC83xx_ESDHC_ADDR --CONFIG_SYS_MPC83xx_ESDHC_OFFSET --CONFIG_SYS_MPC85xx_DMA --CONFIG_SYS_MPC85xx_DMA1_OFFSET --CONFIG_SYS_MPC85xx_DMA2_OFFSET --CONFIG_SYS_MPC85xx_DMA3_OFFSET --CONFIG_SYS_MPC85xx_DMA_ADDR --CONFIG_SYS_MPC85xx_DMA_OFFSET --CONFIG_SYS_MPC85xx_ECM_ADDR --CONFIG_SYS_MPC85xx_ECM_OFFSET --CONFIG_SYS_MPC85xx_ESDHC_ADDR --CONFIG_SYS_MPC85xx_ESDHC_OFFSET --CONFIG_SYS_MPC85xx_ESPI_ADDR --CONFIG_SYS_MPC85xx_ESPI_OFFSET --CONFIG_SYS_MPC85xx_GPIO_ADDR --CONFIG_SYS_MPC85xx_GPIO_OFFSET --CONFIG_SYS_MPC85xx_GUTS_ADDR --CONFIG_SYS_MPC85xx_GUTS_OFFSET --CONFIG_SYS_MPC85xx_IFC_OFFSET --CONFIG_SYS_MPC85xx_L2_ADDR --CONFIG_SYS_MPC85xx_L2_OFFSET --CONFIG_SYS_MPC85xx_LBC_OFFSET --CONFIG_SYS_MPC85xx_PCI1_OFFSET --CONFIG_SYS_MPC85xx_PCI2_OFFSET --CONFIG_SYS_MPC85xx_PCIE --CONFIG_SYS_MPC85xx_PCIE1_OFFSET --CONFIG_SYS_MPC85xx_PCIE2_OFFSET --CONFIG_SYS_MPC85xx_PCIE3_OFFSET --CONFIG_SYS_MPC85xx_PCIE4_OFFSET --CONFIG_SYS_MPC85xx_PCIX2_ADDR --CONFIG_SYS_MPC85xx_PCIX2_OFFSET --CONFIG_SYS_MPC85xx_PCIX_ADDR --CONFIG_SYS_MPC85xx_PCIX_OFFSET --CONFIG_SYS_MPC85xx_PIC_OFFSET --CONFIG_SYS_MPC85xx_QE_OFFSET --CONFIG_SYS_MPC85xx_SATA --CONFIG_SYS_MPC85xx_SATA1_ADDR --CONFIG_SYS_MPC85xx_SATA1_OFFSET --CONFIG_SYS_MPC85xx_SATA2_ADDR --CONFIG_SYS_MPC85xx_SATA2_OFFSET --CONFIG_SYS_MPC85xx_SCFG --CONFIG_SYS_MPC85xx_SCFG_OFFSET --CONFIG_SYS_MPC85xx_SERDES1_ADDR --CONFIG_SYS_MPC85xx_SERDES1_OFFSET --CONFIG_SYS_MPC85xx_SERDES2_ADDR --CONFIG_SYS_MPC85xx_SERDES2_OFFSET --CONFIG_SYS_MPC85xx_TDM_OFFSET --CONFIG_SYS_MPC85xx_USB --CONFIG_SYS_MPC85xx_USB1_ADDR --CONFIG_SYS_MPC85xx_USB1_OFFSET --CONFIG_SYS_MPC85xx_USB1_PHY_ADDR --CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET --CONFIG_SYS_MPC85xx_USB2_ADDR --CONFIG_SYS_MPC85xx_USB2_OFFSET --CONFIG_SYS_MPC85xx_USB2_PHY_ADDR --CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET --CONFIG_SYS_MPC8xxx_DDR2_OFFSET --CONFIG_SYS_MPC8xxx_DDR3_OFFSET --CONFIG_SYS_MPC8xxx_DDR_OFFSET --CONFIG_SYS_MPC8xxx_PIC_ADDR CONFIG_SYS_MRAM_BASE --CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST CONFIG_SYS_NAND_AMASK CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND_BASE2 @@@ -991,7 -991,7 +657,6 @@@ CONFIG_SYS_NAND_U_BOOT_DS CONFIG_SYS_NAND_U_BOOT_RELOC_SP CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_NAND_U_BOOT_START --CONFIG_SYS_NONCACHED_MEMORY CONFIG_SYS_NOR0_CSPR CONFIG_SYS_NOR0_CSPR_EARLY CONFIG_SYS_NOR0_CSPR_EXT