From: Sumit Garg <sumit.garg@linaro.org>
Date: Thu, 4 Aug 2022 14:27:16 +0000 (+0530)
Subject: dts: qcs404-evb: Add USB controller and PHY nodes
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=0c1eab6f759c6abe809bc68c44192924b1d2522a;p=u-boot.git

dts: qcs404-evb: Add USB controller and PHY nodes

QCS404 SoC provides support for two USB controllers: one USB3 and the
other one being USB2. The USB3 controller supports further 2 PHY: one high
speed PHY and the other super speed PHY. The USB2 controller supports a
single high speed PHY. So add corresponding DT nodes.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---

diff --git a/arch/arm/dts/qcs404-evb.dts b/arch/arm/dts/qcs404-evb.dts
index 3166b265ed..719e6a25fb 100644
--- a/arch/arm/dts/qcs404-evb.dts
+++ b/arch/arm/dts/qcs404-evb.dts
@@ -52,6 +52,7 @@
 			reg = <0x1800000 0x80000>;
 			#address-cells = <0x1>;
 			#size-cells = <0x0>;
+			#clock-cells = <1>;
 		};
 
 		reset: gcc-reset@1800000 {
@@ -81,6 +82,92 @@
 			mmc-ddr-1_8v;
 			mmc-hs400-1_8v;
 		};
+
+		usb3_phy: phy@78000 {
+			compatible = "qcom,usb-ss-28nm-phy";
+			#phy-cells = <0>;
+			reg = <0x78000 0x400>;
+			clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
+				 <&gcc GCC_USB3_PHY_PIPE_CLK>;
+			clock-names = "ahb", "pipe";
+			resets = <&reset GCC_USB3_PHY_BCR>,
+				 <&reset GCC_USB3PHY_PHY_BCR>;
+			reset-names = "com", "phy";
+		};
+
+		usb2_phy_prim: phy@7a000 {
+			compatible = "qcom,usb-hs-28nm-femtophy";
+			#phy-cells = <0>;
+			reg = <0x7a000 0x200>;
+			clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
+				 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
+			clock-names = "ahb", "sleep";
+			resets = <&reset GCC_USB_HS_PHY_CFG_AHB_BCR>,
+				 <&reset GCC_USB2A_PHY_BCR>;
+			reset-names = "phy", "por";
+		};
+
+		usb2_phy_sec: phy@7c000 {
+			compatible = "qcom,usb-hs-28nm-femtophy";
+			#phy-cells = <0>;
+			reg = <0x7c000 0x200>;
+			clocks = <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
+				 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
+			clock-names = "ahb", "sleep";
+			resets = <&reset GCC_QUSB2_PHY_BCR>,
+				 <&reset GCC_USB2_HS_PHY_ONLY_BCR>;
+			reset-names = "phy", "por";
+		};
+
+		usb3: usb@7678800 {
+			compatible = "qcom,dwc3";
+			reg = <0x7678800 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			clocks = <&gcc GCC_USB30_MASTER_CLK>,
+				 <&gcc GCC_SYS_NOC_USB3_CLK>,
+				 <&gcc GCC_USB30_SLEEP_CLK>,
+				 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
+			clock-names = "core", "iface", "sleep", "mock_utmi";
+
+			dwc3@7580000 {
+				compatible = "snps,dwc3";
+				reg = <0x7580000 0xcd00>;
+				phys = <&usb2_phy_prim>, <&usb3_phy>;
+				phy-names = "usb2-phy", "usb3-phy";
+				dr_mode = "host";
+				snps,has-lpm-erratum;
+				snps,hird-threshold = /bits/ 8 <0x10>;
+				snps,usb3_lpm_capable;
+				maximum-speed = "super-speed";
+			};
+		};
+
+		usb2: usb@79b8800 {
+			compatible = "qcom,dwc3";
+			reg = <0x79b8800 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>,
+				 <&gcc GCC_PCNOC_USB2_CLK>,
+				 <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>,
+				 <&gcc GCC_USB20_MOCK_UTMI_CLK>;
+			clock-names = "core", "iface", "sleep", "mock_utmi";
+
+			dwc3@78c0000 {
+				compatible = "snps,dwc3";
+				reg = <0x78c0000 0xcc00>;
+				phys = <&usb2_phy_sec>;
+				phy-names = "usb2-phy";
+				dr_mode = "peripheral";
+				snps,has-lpm-erratum;
+				snps,hird-threshold = /bits/ 8 <0x10>;
+				snps,usb3_lpm_capable;
+				maximum-speed = "high-speed";
+			};
+		};
 	};
 };