From: Simon Glass <sjg@chromium.org>
Date: Wed, 4 Nov 2020 16:57:34 +0000 (-0700)
Subject: x86: Define the Chrome OS GNVS region
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=08059c9c02b1e87add0f2409d15ab5cdc745b6fd;p=u-boot.git

x86: Define the Chrome OS GNVS region

It is not possible to boot Chrome OS properly without passing some basic
information from U-Boot. This applies even if verified boot is not being
used. Add a structure definition for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

diff --git a/arch/x86/include/asm/intel_gnvs.h b/arch/x86/include/asm/intel_gnvs.h
index c1e9d65779..632307427c 100644
--- a/arch/x86/include/asm/intel_gnvs.h
+++ b/arch/x86/include/asm/intel_gnvs.h
@@ -9,6 +9,55 @@
 #ifndef _INTEL_GNVS_H_
 #define _INTEL_GNVS_H_
 
+/*
+ * The chromeos_acpi portion of ACPI GNVS is assumed to live from offset
+ * 0x100 - 0x1000.  When defining acpi_global_nvs, use check_member
+ * to ensure that it is properly aligned:
+ *
+ *   check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+ */
+#define GNVS_CHROMEOS_ACPI_OFFSET 0x100
+
+enum {
+	CHSW_RECOVERY_X86 =		BIT(1),
+	CHSW_RECOVERY_EC =		BIT(2),
+	CHSW_DEVELOPER_SWITCH =		BIT(5),
+	CHSW_FIRMWARE_WP =		BIT(9),
+};
+
+enum {
+	FIRMWARE_TYPE_AUTO_DETECT = -1,
+	FIRMWARE_TYPE_RECOVERY = 0,
+	FIRMWARE_TYPE_NORMAL = 1,
+	FIRMWARE_TYPE_DEVELOPER = 2,
+	FIRMWARE_TYPE_NETBOOT = 3,
+	FIRMWARE_TYPE_LEGACY = 4,
+};
+
+struct __packed chromeos_acpi_gnvs {
+	/* ChromeOS-specific */
+	u32	boot_reason;	/* 00 boot reason */
+	u32	active_main_fw;	/* 04 (0=recovery, 1=A, 2=B) */
+	u32	activeec_fw;	/* 08 (0=RO, 1=RW) */
+	u16	switches;	/* 0c CHSW */
+	u8	vbt4[256];	/* 0e HWID */
+	u8	vbt5[64];	/* 10e FWID */
+	u8	vbt6[64];	/* 14e FRID - 275 */
+	u32	main_fw_type;	/* 18e (2 = developer mode) */
+	u32	vbt8;		/* 192 recovery reason */
+	u32	vbt9;		/* 196 fmap base address */
+	u8	vdat[3072];	/* 19a VDAT space filled by verified boot */
+	u32	vbt10;		/* d9a smbios bios version */
+	u32	mehh[8];	/* d9e management engine hash */
+	u32	ramoops_base;	/* dbe ramoops base address */
+	u32	ramoops_len;	/* dc2 ramoops length */
+	u32	vpd_ro_base;	/* dc6 pointer to RO_VPD */
+	u32	vpd_ro_size;	/* dca size of RO_VPD */
+	u32	vpd_rw_base;	/* dce pointer to RW_VPD */
+	u32	vpd_rw_size;	/* dd2 size of RW_VPD */
+	u8	pad[298];	/* dd6-eff */
+};
+
 struct __packed acpi_global_nvs {
 	/* Miscellaneous */
 	u8	pcnt; /* 0x00 - Processor Count */
@@ -31,7 +80,7 @@ struct __packed acpi_global_nvs {
 	u8	unused1[0x100 - 0x3d];		/* Pad out to 256 bytes */
 #ifdef CONFIG_CHROMEOS
 	/* ChromeOS-specific (0x100 - 0xfff) */
-	struct chromeos_acpi chromeos;
+	struct chromeos_acpi_gnvs chromeos;
 #else
 	u8	unused2[0x1000 - 0x100];	/* Pad out to 4096 bytes */
 #endif