From: Marek Behún <marek.behun@nic.cz>
Date: Tue, 23 Jul 2019 14:49:32 +0000 (+0200)
Subject: spi: mvebu_a3700_spi: Fix clock prescale computation
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=07a5cb9d3b9bf9bca9ca207b82f92eac73cbdda8;p=u-boot.git

spi: mvebu_a3700_spi: Fix clock prescale computation

The prescaler value computation can yield wrong result if given 0x1f at
the beginning: the value is computed to be 0x20, but the maximum value
the register can hold 0x1f, so the actual stored value in this case is
0, which is obviously wrong.
Set the upper bound of the value to 0x1f with the min macro.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
---

diff --git a/drivers/spi/mvebu_a3700_spi.c b/drivers/spi/mvebu_a3700_spi.c
index feeafdceaa..99ad505f24 100644
--- a/drivers/spi/mvebu_a3700_spi.c
+++ b/drivers/spi/mvebu_a3700_spi.c
@@ -181,10 +181,9 @@ static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
 	data = readl(&reg->cfg);
 
 	prescale = DIV_ROUND_UP(clk_get_rate(&plat->clk), hz);
-	if (prescale > 0x1f)
-		prescale = 0x1f;
-	else if (prescale > 0xf)
+	if (prescale > 0xf)
 		prescale = 0x10 + (prescale + 1) / 2;
+	prescale = min(prescale, 0x1fu);
 
 	data &= ~MVEBU_SPI_A3700_CLK_PRESCALE_MASK;
 	data |= prescale & MVEBU_SPI_A3700_CLK_PRESCALE_MASK;