mx53: Allow IPUv3 driver to also work on mx53

Adjust the IPU base registers so that ipuv3 driver can work on both mx51 and
mx53 SoCs.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index cef419077e6520720fc8d3c51e559df38ab7fb60..88fb7cb63d1f2e1681807a6f9e6b15b8260c042b 100644 (file)
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -25,7 +25,8 @@
 
 #if defined(CONFIG_MX51)
 #define IRAM_BASE_ADDR         0x1FFE0000      /* internal ram */
-#define IPU_CTRL_BASE_ADDR     0x40000000
+#define IPU_SOC_BASE_ADDR      0x40000000
+#define IPU_SOC_OFFSET         0x1E000000
 #define SPBA0_BASE_ADDR         0x70000000
 #define AIPS1_BASE_ADDR         0x73F00000
 #define AIPS2_BASE_ADDR         0x83F00000
@@ -34,7 +35,8 @@
 #define NFC_BASE_ADDR_AXI       0xCFFF0000
 #define CS1_BASE_ADDR           0xB8000000
 #elif defined(CONFIG_MX53)
-#define IPU_CTRL_BASE_ADDR      0x18000000
+#define IPU_SOC_BASE_ADDR      0x18000000
+#define IPU_SOC_OFFSET         0x06000000
 #define SPBA0_BASE_ADDR         0x50000000
 #define AIPS1_BASE_ADDR         0x53F00000
 #define AIPS2_BASE_ADDR         0x63F00000
@@ -48,6 +50,8 @@
 #error "CPU_TYPE not defined"
 #endif
 
+#define IPU_CTRL_BASE_ADDR     IPU_SOC_BASE_ADDR + IPU_SOC_OFFSET
+
 #define IRAM_SIZE              0x00020000      /* 128 KB */
 
 /*

diff --git a/drivers/video/ipu_regs.h b/drivers/video/ipu_regs.h
index 9964c2039c966d0048ea83a22d44235bca318946..93b195f2ce15c3949a0f99644014fc02a710cf55 100644 (file)
--- a/drivers/video/ipu_regs.h
+++ b/drivers/video/ipu_regs.h
@@ -33,27 +33,27 @@
 #define IPU_DISP0_BASE         0x00000000
 #define IPU_MCU_T_DEFAULT      8
 #define IPU_DISP1_BASE         (IPU_MCU_T_DEFAULT << 25)
-#define IPU_CM_REG_BASE                0x1E000000
-#define IPU_STAT_REG_BASE      0x1E000200
-#define IPU_IDMAC_REG_BASE     0x1E008000
-#define IPU_ISP_REG_BASE       0x1E010000
-#define IPU_DP_REG_BASE                0x1E018000
-#define IPU_IC_REG_BASE                0x1E020000
-#define IPU_IRT_REG_BASE       0x1E028000
-#define IPU_CSI0_REG_BASE      0x1E030000
-#define IPU_CSI1_REG_BASE      0x1E038000
-#define IPU_DI0_REG_BASE       0x1E040000
-#define IPU_DI1_REG_BASE       0x1E048000
-#define IPU_SMFC_REG_BASE      0x1E050000
-#define IPU_DC_REG_BASE                0x1E058000
-#define IPU_DMFC_REG_BASE      0x1E060000
-#define IPU_CPMEM_REG_BASE     0x1F000000
-#define IPU_LUT_REG_BASE       0x1F020000
-#define IPU_SRM_REG_BASE       0x1F040000
-#define IPU_TPM_REG_BASE       0x1F060000
-#define IPU_DC_TMPL_REG_BASE   0x1F080000
-#define IPU_ISP_TBPR_REG_BASE  0x1F0C0000
-#define IPU_VDI_REG_BASE       0x1E068000
+#define IPU_CM_REG_BASE                0x00000000
+#define IPU_STAT_REG_BASE      0x00000200
+#define IPU_IDMAC_REG_BASE     0x00008000
+#define IPU_ISP_REG_BASE       0x00010000
+#define IPU_DP_REG_BASE                0x00018000
+#define IPU_IC_REG_BASE                0x00020000
+#define IPU_IRT_REG_BASE       0x00028000
+#define IPU_CSI0_REG_BASE      0x00030000
+#define IPU_CSI1_REG_BASE      0x00038000
+#define IPU_DI0_REG_BASE       0x00040000
+#define IPU_DI1_REG_BASE       0x00048000
+#define IPU_SMFC_REG_BASE      0x00050000
+#define IPU_DC_REG_BASE                0x00058000
+#define IPU_DMFC_REG_BASE      0x00060000
+#define IPU_CPMEM_REG_BASE     0x01000000
+#define IPU_LUT_REG_BASE       0x01020000
+#define IPU_SRM_REG_BASE       0x01040000
+#define IPU_TPM_REG_BASE       0x01060000
+#define IPU_DC_TMPL_REG_BASE   0x01080000
+#define IPU_ISP_TBPR_REG_BASE  0x010C0000
+#define IPU_VDI_REG_BASE       0x00680000
 
 
 extern u32 *ipu_dc_tmpl_reg;