fm_info_set_mdio(i,
miiphy_get_dev_by_name("HYDRA_RGMII_MDIO"));
break;
- case PHY_INTERFACE_MODE_NONE:
+ case PHY_INTERFACE_MODE_NA:
fm_info_set_phy_address(i, 0);
break;
default:
fm_info_set_mdio(i,
miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
break;
- case PHY_INTERFACE_MODE_NONE:
+ case PHY_INTERFACE_MODE_NA:
fm_info_set_phy_address(i, 0);
break;
default:
fm_info_set_mdio(i,
miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
break;
- case PHY_INTERFACE_MODE_NONE:
+ case PHY_INTERFACE_MODE_NA:
fm_info_set_phy_address(i, 0);
break;
default:
case PHY_INTERFACE_MODE_QSGMII:
fm_info_set_phy_address(i, 0);
break;
- case PHY_INTERFACE_MODE_NONE:
+ case PHY_INTERFACE_MODE_NA:
fm_info_set_phy_address(i, 0);
break;
default:
break;
}
if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII ||
- fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NONE)
+ fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NA)
fm_info_set_mdio(i, NULL);
else
fm_info_set_mdio(i,
mode = ofnode_read_string(node, "phy-connection-type");
if (!mode)
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
for (i = 0; i < PHY_INTERFACE_MODE_MAX; i++)
if (!strcmp(mode, phy_interface_strings[i]))
debug("%s: Invalid PHY interface '%s'\n", __func__, mode);
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
return ret;
pdata->phy_interface = dev_read_phy_mode(dev);
- if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
return 0;
struct eth_pdata *pdata = dev_get_plat(dev);
pdata->phy_interface = dev_read_phy_mode(dev);
- if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
return 0;
/* get phy mode */
pdata->phy_interface = dev_read_phy_mode(dev);
- if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -ENODEV;
/* get phy */
/* Get phy mode from DT */
pdata->phy_interface = dev_read_phy_mode(dev);
- if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
pdata->iobase = dev_read_addr(dev);
pdata->phy_interface = dev_read_phy_mode(dev);
- if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
interface = eqos->config->interface(dev);
- if (interface == PHY_INTERFACE_MODE_NONE) {
+ if (interface == PHY_INTERFACE_MODE_NA) {
pr_err("Invalid PHY interface\n");
return -EINVAL;
}
interface = eqos->config->interface(dev);
- if (interface == PHY_INTERFACE_MODE_NONE) {
+ if (interface == PHY_INTERFACE_MODE_NA) {
pr_err("Invalid PHY interface\n");
return -EINVAL;
}
priv->eth = (struct ethernet_regs *)pdata->iobase;
pdata->phy_interface = dev_read_phy_mode(dev);
- if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
#ifdef CONFIG_DM_REGULATOR
#endif
if (is_device_disabled(port))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
/*B4860 has two 10Gig Mac*/
if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
(port == FM1_DTSEC2) ||
(port == FM1_DTSEC3) ||
(port == FM1_DTSEC4))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
}
}
return PHY_INTERFACE_MODE_SGMII;
break;
default:
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
/*
* Determine if an interface is actually active based on HW config
- * we expect fman_port_enet_if() to report PHY_INTERFACE_MODE_NONE if
+ * we expect fman_port_enet_if() to report PHY_INTERFACE_MODE_NA if
* the interface is not active based on HW cfg of the SoC
*/
void fman_enet_init(void)
phy_interface_t enet_if;
enet_if = fman_port_enet_if(fm_info[i].port);
- if (enet_if != PHY_INTERFACE_MODE_NONE) {
+ if (enet_if != PHY_INTERFACE_MODE_NA) {
fm_info[i].enabled = 1;
fm_info[i].enet_if = enet_if;
} else {
int i = fm_port_to_index(port);
if (i == -1)
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if (fm_info[i].enabled)
return fm_info[i].enet_if;
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
static void
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
return PHY_INTERFACE_MODE_XGMII;
if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9)))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if (port == FM1_DTSEC3)
if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
break;
}
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
return PHY_INTERFACE_MODE_XGMII;
if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9)))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if ((port == FM1_10GEC2) && (is_serdes_configured(XFI_FM1_MAC10)))
return PHY_INTERFACE_MODE_XGMII;
if ((port == FM1_DTSEC10) && (is_serdes_configured(XFI_FM1_MAC10)))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if (port == FM1_DTSEC3)
if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
break;
}
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
u32 pordevsr = in_be32(&gur->pordevsr);
if (is_device_disabled(port))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
/* DTSEC1 can be SGMII, RGMII or RMII */
if (port == FM1_DTSEC1) {
return PHY_INTERFACE_MODE_RGMII;
}
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
if (is_device_disabled(port))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
return PHY_INTERFACE_MODE_XGMII;
return PHY_INTERFACE_MODE_SGMII;
break;
default:
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
if (is_device_disabled(port))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
return PHY_INTERFACE_MODE_XGMII;
return PHY_INTERFACE_MODE_SGMII;
break;
default:
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
if (is_device_disabled(port))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
return PHY_INTERFACE_MODE_XGMII;
return PHY_INTERFACE_MODE_SGMII;
break;
default:
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC1)))
return PHY_INTERFACE_MODE_XGMII;
break;
}
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
return PHY_INTERFACE_MODE_SGMII;
break;
default:
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
((is_serdes_configured(XAUI_FM1_MAC9)) ||
return PHY_INTERFACE_MODE_SGMII;
break;
default:
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
((is_serdes_configured(XAUI_FM1_MAC9)) ||
if ((port == FM1_DTSEC9 || port == FM1_DTSEC10) &&
((is_serdes_configured(XFI_FM1_MAC9)) ||
(is_serdes_configured(XFI_FM1_MAC10))))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if ((port == FM2_10GEC1 || port == FM2_10GEC2) &&
((is_serdes_configured(XAUI_FM2_MAC9)) ||
break;
}
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
}
priv->if_type = dev_read_phy_mode(dev);
- if (priv->if_type == PHY_INTERFACE_MODE_NONE) {
+ if (priv->if_type == PHY_INTERFACE_MODE_NA) {
enetc_dbg(dev,
"phy-mode property not found, defaulting to SGMII\n");
priv->if_type = PHY_INTERFACE_MODE_SGMII;
pdata->iobase = dev_read_addr(dev);
pdata->phy_interface = dev_read_phy_mode(dev);
- if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
priv->macif_ctrl = dev_remap_addr_index(dev, 1);
priv->phyintf = dev_read_phy_mode(dev);
- if (priv->phyintf == PHY_INTERFACE_MODE_NONE)
+ if (priv->phyintf == PHY_INTERFACE_MODE_NA)
return -ENODEV;
phy_node = dev_read_subnode(dev, "phy");
int phy_mode = -1;
phy_mode = dev_read_phy_mode(dev);
- if (phy_mode == PHY_INTERFACE_MODE_NONE) {
+ if (phy_mode == PHY_INTERFACE_MODE_NA) {
dev_err(dev, "incorrect phy mode\n");
return -EINVAL;
}
__weak phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtc)
{
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
void wriop_init_dpmac(int sd, int dpmac_id, int lane_prtcl)
dpmac_info[dpmac_id].enabled = 0;
dpmac_info[dpmac_id].id = 0;
- dpmac_info[dpmac_id].enet_if = PHY_INTERFACE_MODE_NONE;
+ dpmac_info[dpmac_id].enet_if = PHY_INTERFACE_MODE_NA;
enet_if = wriop_dpmac_enet_if(dpmac_id, lane_prtcl);
- if (enet_if != PHY_INTERFACE_MODE_NONE) {
+ if (enet_if != PHY_INTERFACE_MODE_NA) {
dpmac_info[dpmac_id].enabled = 1;
dpmac_info[dpmac_id].id = dpmac_id;
dpmac_info[dpmac_id].enet_if = enet_if;
int i = wriop_dpmac_to_index(dpmac_id);
if (i == -1)
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if (dpmac_info[i].enabled)
return dpmac_info[i].enet_if;
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
enum srds_prtcl;
if (is_device_disabled(dpmac_id + 1))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
switch (lane_prtcl) {
case SGMII1:
if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_B)
return PHY_INTERFACE_MODE_QSGMII;
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
enum srds_prtcl;
if (is_device_disabled(dpmac_id + 1))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII16)
return PHY_INTERFACE_MODE_SGMII;
if (lane_prtcl >= QSGMII_A && lane_prtcl <= QSGMII_D)
return PHY_INTERFACE_MODE_QSGMII;
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
enum srds_prtcl;
if (is_device_disabled(dpmac_id))
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18)
return PHY_INTERFACE_MODE_SGMII;
if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2)
return PHY_INTERFACE_MODE_CAUI4;
- return PHY_INTERFACE_MODE_NONE;
+ return PHY_INTERFACE_MODE_NA;
}
#ifdef CONFIG_SYS_FSL_HAS_RGMII
int ret;
macb->phy_interface = dev_read_phy_mode(dev);
- if (macb->phy_interface == PHY_INTERFACE_MODE_NONE)
+ if (macb->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
/* Read phyaddr from DT */
phy = phy_connect(priv->ports[i].bus,
priv->ports[i].phy_addr, dev,
- PHY_INTERFACE_MODE_NONE);
+ PHY_INTERFACE_MODE_NA);
if (phy)
board_phy_config(phy);
}
phy = phy_connect(priv->ports[i].bus,
priv->ports[i].phy_addr, dev,
- PHY_INTERFACE_MODE_NONE);
+ PHY_INTERFACE_MODE_NA);
if (phy && i >= MAX_INT_PORT)
board_phy_config(phy);
}
phy = phy_connect(priv->ports[i].bus,
priv->ports[i].phy_addr, dev,
- PHY_INTERFACE_MODE_NONE);
+ PHY_INTERFACE_MODE_NA);
if (phy && external_bus(priv, i))
board_phy_config(phy);
}
phy = phy_connect(priv->ports[i].bus,
priv->ports[i].phy_addr, dev,
- PHY_INTERFACE_MODE_NONE);
+ PHY_INTERFACE_MODE_NA);
if (phy)
board_phy_config(phy);
}
continue;
phy_connect(priv->ports[i].bus, priv->ports[i].phy_addr, dev,
- PHY_INTERFACE_MODE_NONE);
+ PHY_INTERFACE_MODE_NA);
}
return 0;
case PHY_INTERFACE_MODE_RGMII:
ge_mode = MT7620_SYSC_GE_RGMII;
break;
- case PHY_INTERFACE_MODE_NONE:
+ case PHY_INTERFACE_MODE_NA:
if (gmac == 2)
ge_mode = MT7620_SYSC_GE_ESW_PHY;
else
{
u32 pmcr;
- if (port_cfg->mode == PHY_INTERFACE_MODE_NONE) {
+ if (port_cfg->mode == PHY_INTERFACE_MODE_NA) {
if (port == 5) {
gsw_write(priv, GSW_PMCR(port), FORCE_MODE);
return;
{
int phy_addr_st, phy_addr_end;
- if (priv->port_cfg[0].mode == PHY_INTERFACE_MODE_NONE)
+ if (priv->port_cfg[0].mode == PHY_INTERFACE_MODE_NA)
priv->ephy_num = NUM_FE_PHYS;
else
priv->ephy_num = NUM_FE_PHYS - 1;
case PHY_INTERFACE_MODE_MII:
case PHY_INTERFACE_MODE_RMII:
case PHY_INTERFACE_MODE_RGMII:
- case PHY_INTERFACE_MODE_NONE:
+ case PHY_INTERFACE_MODE_NA:
break;
default:
dev_err(priv->dev, "mt7620_eth: unsupported phy-mode\n");
if (ret)
return ret;
} else {
- priv->port_cfg[0].mode = PHY_INTERFACE_MODE_NONE;
+ priv->port_cfg[0].mode = PHY_INTERFACE_MODE_NA;
}
subnode = ofnode_find_subnode(dev_ofnode(dev), "port5");
if (ofnode_valid(subnode))
return mt7620_eth_parse_gsw_port(priv, 1, subnode);
- priv->port_cfg[1].mode = PHY_INTERFACE_MODE_NONE;
+ priv->port_cfg[1].mode = PHY_INTERFACE_MODE_NA;
return 0;
}
/* Interface mode is required */
pdata->phy_interface = dev_read_phy_mode(dev);
priv->phy_interface = pdata->phy_interface;
- if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE) {
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) {
printf("error: phy-mode is not set\n");
return -EINVAL;
}
/* Get phy-mode / phy_interface from DT */
pdata->phy_interface = dev_read_phy_mode(dev);
- if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
pdata->phy_interface = PHY_INTERFACE_MODE_GMII;
dmvgbe->phy_interface = pdata->phy_interface;
/* Get phy-mode / phy_interface from DT */
pdata->phy_interface = dev_read_phy_mode(dev);
- if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
return 0;
}
port->phy_interface = dev_read_phy_mode(dev);
- if (port->phy_interface == PHY_INTERFACE_MODE_NONE) {
+ if (port->phy_interface == PHY_INTERFACE_MODE_NA) {
dev_err(dev, "incorrect phy mode\n");
return -EINVAL;
}
/* get phy mode */
pdata->phy_interface = dev_read_phy_mode(dev);
- if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
/* get phy addr */
pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
pdata->phy_interface = dev_read_phy_mode(dev);
- if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
return 0;
pdata->iobase = dev_read_addr(dev);
pdata->phy_interface = dev_read_phy_mode(dev);
- if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
pdata->max_speed = 1000;
pdata->iobase = dev_read_addr(dev);
pdata->phy_interface = dev_read_phy_mode(dev);
- if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
pdata->max_speed = 1000;
pdata->iobase = dev_read_addr(dev);
pdata->phy_interface = dev_read_phy_mode(dev);
- if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
pdata->max_speed = 0;
priv->eeprom_base = dev_read_addr_index(dev, 1) - EERPROM_MAP_OFFSET;
pdata->phy_interface = dev_read_phy_mode(dev);
- if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
pdata->phy_interface = dev_read_phy_mode(dev);
printf("phy interface%d\n", pdata->phy_interface);
- if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
if (priv->variant == H3_EMAC) {
dev_read_u32(dev, "reg", &priv->port_id);
pdata->phy_interface = dev_read_phy_mode(dev);
- if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE) {
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) {
dev_err(dev, "Invalid PHY mode, port %u\n", priv->port_id);
return -EINVAL;
}
}
pdata->phy_interface = data->slave_data[data->active_slave].phy_if;
- if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
return 0;
priv->has_mdio = true;
} else if (priv->link_type == LINK_TYPE_RGMII_LINK_MAC_PHY) {
priv->phy_if = ofnode_read_phy_mode(offset_to_ofnode(slave));
- if (priv->phy_if == PHY_INTERFACE_MODE_NONE)
+ if (priv->phy_if == PHY_INTERFACE_MODE_NA)
priv->phy_if = PHY_INTERFACE_MODE_RGMII;
pdata->phy_interface = priv->phy_if;
priv->tbiaddr = tbiaddr;
pdata->phy_interface = dev_read_phy_mode(dev);
- if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
pdata->phy_interface = tsec_get_interface(priv);
priv->interface = pdata->phy_interface;
}
pdata->phy_interface = dev_read_phy_mode(dev);
- if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
plat->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
}
pdata->phy_interface = dev_read_phy_mode(dev);
- if (pdata->phy_interface == PHY_INTERFACE_MODE_NONE)
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
return -EINVAL;
priv->interface = pdata->phy_interface;
* returns the corresponding PHY interface type.
*
* @mac_node: ofnode containing the property
- * Return: one of PHY_INTERFACE_MODE_* constants, PHY_INTERFACE_MODE_NONE on
+ * Return: one of PHY_INTERFACE_MODE_* constants, PHY_INTERFACE_MODE_NA on
* error
*/
phy_interface_t ofnode_read_phy_mode(ofnode mac_node);
* returns the corresponding PHY interface type.
*
* @dev: device representing the MAC
- * Return: one of PHY_INTERFACE_MODE_* constants, PHY_INTERFACE_MODE_NONE on
+ * Return: one of PHY_INTERFACE_MODE_* constants, PHY_INTERFACE_MODE_NA on
* error
*/
phy_interface_t dev_read_phy_mode(const struct udevice *dev);
#define FM_ETH_INFO_INITIALIZER(idx, pregs) \
.fm = idx, \
.phy_regs = (void *)pregs, \
- .enet_if = PHY_INTERFACE_MODE_NONE, \
+ .enet_if = PHY_INTERFACE_MODE_NA, \
#ifdef CONFIG_SYS_FMAN_V3
#define FM_DTSEC_INFO_INITIALIZER(idx, n) \
PHY_INTERFACE_MODE_NCSI,
PHY_INTERFACE_MODE_10GBASER,
PHY_INTERFACE_MODE_USXGMII,
- PHY_INTERFACE_MODE_NONE, /* Must be last */
+ PHY_INTERFACE_MODE_NA, /* Must be last */
PHY_INTERFACE_MODE_MAX,
} phy_interface_t;
[PHY_INTERFACE_MODE_NCSI] = "NC-SI",
[PHY_INTERFACE_MODE_10GBASER] = "10gbase-r",
[PHY_INTERFACE_MODE_USXGMII] = "usxgmii",
- [PHY_INTERFACE_MODE_NONE] = "",
+ [PHY_INTERFACE_MODE_NA] = "",
};
/* Backplane modes:
static inline const char *phy_string_for_interface(phy_interface_t i)
{
/* Default to unknown */
- if (i > PHY_INTERFACE_MODE_NONE)
- i = PHY_INTERFACE_MODE_NONE;
+ if (i > PHY_INTERFACE_MODE_NA)
+ i = PHY_INTERFACE_MODE_NA;
return phy_interface_strings[i];
}
.phyaddr = 0, \
.index = idx, \
.phy_regs = NULL, \
- .enet_if = PHY_INTERFACE_MODE_NONE, \
+ .enet_if = PHY_INTERFACE_MODE_NA, \
.bus = NULL, \
.phydev = NULL, \
}
}
interface = dev_read_phy_mode(ethdev);
- if (interface == PHY_INTERFACE_MODE_NONE)
- dev_dbg(ethdev, "can't find interface mode, default to NONE\n");
+ if (interface == PHY_INTERFACE_MODE_NA)
+ dev_dbg(ethdev, "can't find interface mode, default to NA\n");
phy = dm_eth_connect_phy_handle(ethdev, interface);