mips: octeon: dts: Add Octeon 3 cn73xx base dtsi file

This patch adds the base dtsi file for the Octeon 3 cn73xx SoC.

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/MAINTAINERS b/MAINTAINERS
index bde85302eca4e35572c1679e2fdc035e562fb58e..6316c6ca00f8a5e49c9343ce659ca02b32180286 100644 (file)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -775,6 +775,7 @@ M:  Aaron Williams <awilliams@marvell.com>
 S:     Maintained
 F:     arch/mips/mach-octeon/
 F:     arch/mips/include/asm/arch-octeon/
+F:     arch/mips/dts/mrvl,cn73xx.dtsi
 
 MMC
 M:     Peng Fan <peng.fan@nxp.com>

diff --git a/arch/mips/dts/mrvl,cn73xx.dtsi b/arch/mips/dts/mrvl,cn73xx.dtsi
new file mode 100644 (file)
index 0000000..a7bd55f
--- /dev/null
+++ b/arch/mips/dts/mrvl,cn73xx.dtsi
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Marvell / Cavium Inc. CN73xx
+ */
+
+/dts-v1/;
+
+/ {
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       soc0: soc@0 {
+               interrupt-parent = <&ciu3>;
+               compatible = "simple-bus";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges; /* Direct mapping */
+
+               ciu3: interrupt-controller@1010000000000 {
+                       compatible = "cavium,octeon-7890-ciu3";
+                       interrupt-controller;
+                       /*
+                        * Interrupts are specified by two parts:
+                        * 1) Source number (20 significant bits)
+                        * 2) Trigger type: (4 == level, 1 == edge)
+                        */
+                       #address-cells = <0>;
+                       #interrupt-cells = <2>;
+                       reg = <0x10100 0x00000000 0x0 0xb0000000>;
+               };
+
+               bootbus: bootbus@1180000000000 {
+                       compatible = "cavium,octeon-3860-bootbus","simple-bus";
+                       reg = <0x11800 0x00000000 0x0 0x200>;
+                       /* The chip select number and offset */
+                       #address-cells = <2>;
+                       /* The size of the chip select region */
+                       #size-cells = <1>;
+               };
+
+               reset: reset@1180006001600 {
+                       compatible = "mrvl,cn7xxx-rst";
+                       reg = <0x11800 0x06001600 0x0 0x200>;
+               };
+
+               uart0: serial@1180000000800 {
+                       compatible = "cavium,octeon-3860-uart","ns16550";
+                       reg = <0x11800 0x00000800 0x0 0x400>;
+                       clock-frequency = <0>;
+                       current-speed = <115200>;
+                       reg-shift = <3>;
+                       interrupts = <0x08000 4>;
+               };
+
+               uart1: serial@1180000000c00 {
+                       compatible = "cavium,octeon-3860-uart","ns16550";
+                       reg = <0x11800 0x00000c00 0x0 0x400>;
+                       clock-frequency = <0>;
+                       current-speed = <115200>;
+                       reg-shift = <3>;
+                       interrupts = <0x08040 4>;
+               };
+       };
+};