rockchip: rk3588-rock-5b: Enable boot from SPI NOR flash

Add sfc and flash node to device tree and config options to enable
support for booting from SPI NOR flash on Radxa ROCK 5 Model B.

Similar to RK3568 the BootRom in RK3588 can read all data and look for
idbloader at 0x8000, same as on SD and eMMC.

Use the rksd format and modify the mkimage offset to generate a bootable
u-boot-rockchip-spi.bin that can be written to 0x0 of SPI NOR flash. The
FIT image is loaded from 0x60000.

  => sf probe
  SF: Detected mx25u12835f with page size 256 Bytes, erase size 4 KiB, total 16 MiB

  => load mmc 1:1 10000000 u-boot-rockchip-spi.bin
  1492992 bytes read in 129 ms (11 MiB/s)

  => sf update $fileaddr 0 $filesize
  device 0 offset 0x0, size 0x16c800
  1300480 bytes written, 192512 bytes skipped in 11.103s, speed 137694 B/s

The BROM_BOOTSOURCE_ID value read back when booting from SPI flash does
not match the expected value of 3 (SPINOR) used by other SoCs. Instead a
value of 6 is read back, add a new enum value to handle this new
bootsource id.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>

diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
index db342e6a9391fcdd21ad61730365ba87e9cb2775..1cd8a57a6fa603ecb7c4aac944af8c544a478565 100644 (file)
--- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
+++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi
@@ -11,6 +11,7 @@
 / {
        aliases {
                mmc1 = &sdmmc;
+               spi0 = &sfc;
        };
 
        chosen {
@@ -54,6 +55,10 @@
        bootph-all;
 };
 
+&fspim2_pins {
+       bootph-all;
+};
+
 &pcie2x1l2 {
        pinctrl-names = "default";
        pinctrl-0 = <&pcie2x1l2_pins &pcie_reset_h>;
@@ -123,6 +128,25 @@
        pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe &emmc_rstnout>;
 };
 
+&sfc {
+       bootph-pre-ram;
+       u-boot,spl-sfc-no-dma;
+       pinctrl-names = "default";
+       pinctrl-0 = <&fspim2_pins>;
+       #address-cells = <1>;
+       #size-cells = <0>;
+       status = "okay";
+
+       flash@0 {
+               bootph-pre-ram;
+               compatible = "jedec,spi-nor";
+               reg = <0>;
+               spi-max-frequency = <24000000>;
+               spi-rx-bus-width = <4>;
+               spi-tx-bus-width = <1>;
+       };
+};
+
 &uart2m0_xfer {
        bootph-all;
 };

diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index 4fdf97ccac44aef084e8a21395af3e8ffd5521f8..c703e41802b6fa6d163316a486cae8dd37725ec6 100644 (file)
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -165,6 +165,15 @@
                };
        };
 
+       sfc: spi@fe2b0000 {
+               compatible = "rockchip,sfc";
+               reg = <0x0 0xfe2b0000 0x0 0x4000>;
+               interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
+               clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+               clock-names = "clk_sfc", "hclk_sfc";
+               status = "disabled";
+       };
+
        otp: nvmem@fecc0000 {
                compatible = "rockchip,rk3588-otp";
                reg = <0x0 0xfecc0000 0x0 0x400>;
@@ -242,3 +251,14 @@
 &ioc {
        bootph-pre-ram;
 };
+
+#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
+&binman {
+       simple-bin-spi {
+               mkimage {
+                       args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
+                       offset = <0x8000>;
+               };
+       };
+};
+#endif

diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h
index 4276a0f6811a24ff285ecc1bdd964753a2fc37fb..7dab18fbc3fb53bc0da2c64cdb9c6afba6d5a204 100644 (file)
--- a/arch/arm/include/asm/arch-rockchip/bootrom.h
+++ b/arch/arm/include/asm/arch-rockchip/bootrom.h
@@ -48,6 +48,7 @@ enum {
        BROM_BOOTSOURCE_SPINOR = 3,
        BROM_BOOTSOURCE_SPINAND = 4,
        BROM_BOOTSOURCE_SD = 5,
+       BROM_BOOTSOURCE_SPINOR_RK3588 = 6,
        BROM_BOOTSOURCE_USB = 10,
        BROM_LAST_BOOTSOURCE = BROM_BOOTSOURCE_USB
 };

diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c
index 18e67b5ca9b22af3a727cdc74194a6b8a8088b5d..b1f535fad505e5b89bc1acd88dc7c12337ec7960 100644 (file)
--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -41,6 +41,7 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
        [BROM_BOOTSOURCE_EMMC] = "/mmc@fe2e0000",
        [BROM_BOOTSOURCE_SPINOR] = "/spi@fe2b0000/flash@0",
        [BROM_BOOTSOURCE_SD] = "/mmc@fe2c0000",
+       [BROM_BOOTSOURCE_SPINOR_RK3588] = "/spi@fe2b0000/flash@0",
 };
 
 static struct mm_region rk3588_mem_map[] = {

diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index e2d5f9c106508710ab22314aa502ff3684a9d389..c1155c20efa875c3ea15dfc195d4ba11809c63d6 100644 (file)
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -8,15 +8,20 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
+CONFIG_SF_DEFAULT_SPEED=24000000
+CONFIG_SF_DEFAULT_MODE=0x2000
 CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b"
 CONFIG_ROCKCHIP_RK3588=y
 CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x600000
 CONFIG_TARGET_ROCK5B_RK3588=y
 CONFIG_SPL_STACK=0x400000
 CONFIG_DEBUG_UART_BASE=0xFEB50000
 CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0xc00800
 CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
@@ -36,6 +41,8 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
 CONFIG_SPL_ATF=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
@@ -60,6 +67,8 @@ CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_XTX=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_PCIE_DW_ROCKCHIP=y
@@ -72,6 +81,7 @@ CONFIG_SPL_RAM=y
 CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SFC=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y