]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
Convert CONFIG_SYS_83XX_DDR_USES_CS0 to Kconfig
authorTom Rini <trini@konsulko.com>
Sat, 25 Jun 2022 15:02:41 +0000 (11:02 -0400)
committerTom Rini <trini@konsulko.com>
Thu, 7 Jul 2022 13:29:08 +0000 (09:29 -0400)
This converts the following to Kconfig:
   CONFIG_SYS_83XX_DDR_USES_CS0

Signed-off-by: Tom Rini <trini@konsulko.com>
README
arch/powerpc/cpu/mpc83xx/Kconfig
include/configs/MPC837XERDB.h

diff --git a/README b/README
index 6bdfca66d65fbe80f23c5f0ad9d96c4f6cd198cc..efc75a3f75b98c0a43b690b64b9603591385c8d6 100644 (file)
--- a/README
+++ b/README
@@ -2074,10 +2074,6 @@ Low Level (hardware related) configuration options:
 - CONFIG_FSL_DDR_BIST
                Enable built-in memory test for Freescale DDR controllers.
 
-- CONFIG_SYS_83XX_DDR_USES_CS0
-               Only for 83xx systems. If specified, then DDR should
-               be configured using CS0 and CS1 instead of CS2 and CS3.
-
 - CONFIG_RMII
                Enable RMII mode for all FECs.
                Note that this is a global option, we can't
index d1b9ae4c3c9228c688d7912fd922b4a83009f99a..9a31604ba3e6d71622e2fb0ba3d0e8f3cf480e6a 100644 (file)
@@ -11,6 +11,11 @@ config E300
 config SYS_CPU
        default "mpc83xx"
 
+config SYS_83XX_DDR_USES_CS0
+       bool
+       help
+         DDR should be configured using CS0 and CS1 instead of CS2 and CS3.
+
 choice
        prompt "Target select"
        optional
@@ -19,6 +24,7 @@ config TARGET_MPC837XERDB
        bool "Support MPC837XERDB"
        select ARCH_MPC837X
        select BOARD_EARLY_INIT_F
+       select SYS_83XX_DDR_USES_CS0
 
 config TARGET_IDS8313
        bool "Support ids8313"
index 8517b0330f52d23189f8513afa27df743723b846..fc55e5c2f614fc740a33265762d0606139e81d8f 100644 (file)
@@ -61,7 +61,6 @@
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  0x03000000
-#define CONFIG_SYS_83XX_DDR_USES_CS0
 
 #define CONFIG_SYS_DDRCDR_VALUE        (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)