riscv: add run mode configuration for SPL

U-Boot SPL can be run in a different privilege mode from U-Boot proper.
Add new configuration entries for SPL to allow the run mode to be
configured independently of U-Boot proper.

Extend all uses of the CONFIG_RISCV_SMODE and CONFIG_RISCV_MMODE
configuration symbols to also cover the SPL equivalents. Ensure that
files compatible with only one privilege mode are not included in builds
targeting an incompatible privilege mode.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 8cfc7d0faaac1a98a00ac9e1b364f4016a05afaf..b8d01ba8e1733659a012ba4df199f121360879e2 100644 (file)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -113,6 +113,23 @@ config RISCV_SMODE
 
 endchoice
 
+choice
+       prompt "SPL Run Mode"
+       default SPL_RISCV_MMODE
+       depends on SPL
+
+config SPL_RISCV_MMODE
+       bool "Machine"
+       help
+         Choose this option to build U-Boot SPL for RISC-V M-Mode.
+
+config SPL_RISCV_SMODE
+       bool "Supervisor"
+       help
+         Choose this option to build U-Boot SPL for RISC-V S-Mode.
+
+endchoice
+
 config RISCV_ISA_C
        bool "Emit compressed instructions"
        default y
@@ -132,34 +149,40 @@ config 64BIT
 
 config SIFIVE_CLINT
        bool
-       depends on RISCV_MMODE
+       depends on RISCV_MMODE || SPL_RISCV_MMODE
        select REGMAP
        select SYSCON
+       select SPL_REGMAP if SPL
+       select SPL_SYSCON if SPL
        help
          The SiFive CLINT block holds memory-mapped control and status registers
          associated with software and timer interrupts.
 
 config ANDES_PLIC
        bool
-       depends on RISCV_MMODE
+       depends on RISCV_MMODE || SPL_RISCV_MMODE
        select REGMAP
        select SYSCON
+       select SPL_REGMAP if SPL
+       select SPL_SYSCON if SPL
        help
          The Andes PLIC block holds memory-mapped claim and pending registers
          associated with software interrupt.
 
 config ANDES_PLMT
        bool
-       depends on RISCV_MMODE
+       depends on RISCV_MMODE || SPL_RISCV_MMODE
        select REGMAP
        select SYSCON
+       select SPL_REGMAP if SPL
+       select SPL_SYSCON if SPL
        help
          The Andes PLMT block holds memory-mapped mtime register
          associated with timer tick.
 
 config RISCV_RDTIME
        bool
-       default y if RISCV_SMODE
+       default y if RISCV_SMODE || SPL_RISCV_SMODE
        help
          The provides the riscv_get_time() API that is implemented using the
          standard rdtime instruction. This is the case for S-mode U-Boot, and
@@ -189,7 +212,7 @@ config NR_CPUS
 
 config SBI_IPI
        bool
-       default y if RISCV_SMODE
+       default y if RISCV_SMODE || SPL_RISCV_SMODE
        depends on SMP
 
 config XIP

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 6b4b92e6921612828ba6665a3a9e63ae59f5fb83..f4b59cb71d63f1ede1f2bbf2b05126ed5d93fc66 100644 (file)
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -4,8 +4,8 @@ config RISCV_NDS
        imply CPU
        imply CPU_RISCV
        imply RISCV_TIMER
-       imply ANDES_PLIC if RISCV_MMODE
-       imply ANDES_PLMT if RISCV_MMODE
+       imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
+       imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE)
        help
          Run U-Boot on AndeStar V5 platforms and use some specific features
          which are provided by Andes Technology AndeStar V5 families.
@@ -14,7 +14,7 @@ if RISCV_NDS
 
 config RISCV_NDS_CACHE
        bool "AndeStar V5 families specific cache support"
-       depends on RISCV_MMODE
+       depends on RISCV_MMODE || SPL_RISCV_MMODE
        help
          Provide Andes Technology AndeStar V5 families specific cache support.
 

diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 5ca185745eebe551dbc2de14ff26adb05723108b..e457f6acbf166d1dbe112a02bd073411d72c391b 100644 (file)
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -46,13 +46,13 @@ static inline bool supports_extension(char ext)
 
        return false;
 #else  /* !CONFIG_CPU */
-#ifdef CONFIG_RISCV_MMODE
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
        return csr_read(CSR_MISA) & (1 << (ext - 'a'));
-#else  /* !CONFIG_RISCV_MMODE */
+#else  /* !CONFIG_IS_ENABLED(RISCV_MMODE) */
 #warning "There is no way to determine the available extensions in S-mode."
 #warning "Please convert your board to use the RISC-V CPU driver."
        return false;
-#endif /* CONFIG_RISCV_MMODE */
+#endif /* CONFIG_IS_ENABLED(RISCV_MMODE) */
 #endif /* CONFIG_CPU */
 }
 

diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig
index 1d6ab5032da5f766d293e6cff00f66e996c08857..b7552f539f4ca3ffdfb2040b2d1a6e9b2ba0e1ca 100644 (file)
--- a/arch/riscv/cpu/generic/Kconfig
+++ b/arch/riscv/cpu/generic/Kconfig
@@ -8,5 +8,5 @@ config GENERIC_RISCV
        imply CPU
        imply CPU_RISCV
        imply RISCV_TIMER
-       imply SIFIVE_CLINT if RISCV_MMODE
+       imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
        imply CMD_CPU

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index e06db404f5a5bd56800d53d624d4a15a3c42a56b..e82ee9e365a64ff77efe0d77e2dffb10d9741889 100644 (file)
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -39,7 +39,7 @@ secondary_harts_relocation_error:
 .section .text
 .globl _start
 _start:
-#ifdef CONFIG_RISCV_MMODE
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
        csrr    a0, CSR_MHARTID
 #endif
 
@@ -62,7 +62,7 @@ _start:
 
 #ifdef CONFIG_SMP
        /* set xSIE bit to receive IPIs */
-#ifdef CONFIG_RISCV_MMODE
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
        li      t0, MIE_MSIE
 #else
        li      t0, SIE_SSIE
@@ -344,7 +344,7 @@ secondary_hart_loop:
 
 #ifdef CONFIG_SMP
        csrr    t0, MODE_PREFIX(ip)
-#ifdef CONFIG_RISCV_MMODE
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
        andi    t0, t0, MIE_MSIE
 #else
        andi    t0, t0, SIE_SSIE

diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h
index c450eb9103b4dfbe39041338328d32471204d590..a0695da93643b8c07d8e4b20c3b2d2702f799900 100644 (file)
--- a/arch/riscv/include/asm/encoding.h
+++ b/arch/riscv/include/asm/encoding.h
@@ -9,7 +9,7 @@
 
 #include <asm/csr.h>
 
-#ifdef CONFIG_RISCV_SMODE
+#if CONFIG_IS_ENABLED(RISCV_SMODE)
 #define MODE_PREFIX(__suffix)  s##__suffix
 #else
 #define MODE_PREFIX(__suffix)  m##__suffix

diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 6ae6ebbeafdac85a973c558e8eb6245ee007eec0..e4bc5df297ff815ed8aa055cbfc7b58058b81274 100644 (file)
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -10,13 +10,16 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
 obj-$(CONFIG_CMD_GO) += boot.o
 obj-y  += cache.o
-obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
+ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
 obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
 obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
 obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o
+else
+obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
+obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
+endif
 obj-y  += interrupts.o
 obj-y  += reset.o
-obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
 obj-y   += setjmp.o
 obj-$(CONFIG_SMP) += smp.o