The comment says to clear the bypass bit, but in fact it sets it, thus
selecting ref_xtal. And the next line of code does not set the divider
to 12, but to (the reset value of) 1.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
/*
* Enable NAND clock
*/
- /* Clear bypass bit */
+ /* Set bypass bit */
writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
&clkctrl_regs->hw_clkctrl_clkseq_set);
- /* Set GPMI clock to ref_gpmi / 12 */
+ /* Set GPMI clock to ref_xtal / 1 */
clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1);