riscv: fix the wrong swap value register

Not s2 register, t1 register is correct
Fortunately, it works because t1 register has a garbage value

Signed-off-by: Brad Kim <brad.kim@semifive.com>
Reviewed-by: Lukas Auer <lukas@auer.io>
Reviewed-by: Leo Liang <ycliang@andestech.com>

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index bbc737ed9a2193b71fed426ad48c906744881d42..8589509e012eb737d0ec1ba9d5eccf329ad275b8 100644 (file)
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -123,7 +123,7 @@ call_board_init_f_0:
         * wait for initialization to complete.
         */
        la      t0, hart_lottery
-       li      s2, 1
+       li      t1, 1
        amoswap.w s2, t1, 0(t0)
        bnez    s2, wait_for_gd_init
 #else