m68k: Fix incorrect memory access on M5235

The csarX and cscrX registers in the fbcs_t struct are 16-bit for
CONFIG_M5235 and 32-bit wide otherwise. The code in cpu_init.c
accessed them always as 32-bit, effectively creating a wrong memory
access on M5235. Fixed that by choosing out_be16/out_be32 depending
on whether CONFIG_M5235 is defined or not.

Cc: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Vasili Galka <vvv444@gmail.com>

diff --git a/arch/m68k/cpu/mcf523x/cpu_init.c b/arch/m68k/cpu/mcf523x/cpu_init.c
index 5a789540fc93bb4aaf069f2a55fa7689e827f7d1..af1fd560688ed24430356580e9aa3c261e4c4c33 100644 (file)
--- a/arch/m68k/cpu/mcf523x/cpu_init.c
+++ b/arch/m68k/cpu/mcf523x/cpu_init.c
@@ -20,6 +20,13 @@
 #include <asm/fec.h>
 #endif
 
+/* The registers in fbcs_t struct can be 16-bit for CONFIG_M5235 or 32-bit wide otherwise. */
+#ifdef CONFIG_M5235
+#define out_be_fbcs_reg                out_be16
+#else
+#define out_be_fbcs_reg                out_be32
+#endif
+
 /*
  * Breath some life into the CPU...
  *
@@ -45,57 +52,57 @@ void cpu_init_f(void)
        out_8(&gpio->par_cs, 0);
 
 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
-       out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
-       out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
+       out_be_fbcs_reg(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
+       out_be_fbcs_reg(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
        out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
        setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS1);
-       out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
-       out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
+       out_be_fbcs_reg(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
+       out_be_fbcs_reg(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
        out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
        setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS2);
-       out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
-       out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
+       out_be_fbcs_reg(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
+       out_be_fbcs_reg(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
        out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
        setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS3);
-       out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
-       out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
+       out_be_fbcs_reg(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
+       out_be_fbcs_reg(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
        out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
        setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS4);
-       out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
-       out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
+       out_be_fbcs_reg(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
+       out_be_fbcs_reg(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
        out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
        setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS5);
-       out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
-       out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
+       out_be_fbcs_reg(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
+       out_be_fbcs_reg(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
        out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL))
        setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS6);
-       out_be32(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
-       out_be32(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
+       out_be_fbcs_reg(&fbcs->csar6, CONFIG_SYS_CS6_BASE);
+       out_be_fbcs_reg(&fbcs->cscr6, CONFIG_SYS_CS6_CTRL);
        out_be32(&fbcs->csmr6, CONFIG_SYS_CS6_MASK);
 #endif
 
 #if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL))
        setbits_8(&gpio->par_cs, GPIO_PAR_CS_CS7);
-       out_be32(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
-       out_be32(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
+       out_be_fbcs_reg(&fbcs->csar7, CONFIG_SYS_CS7_BASE);
+       out_be_fbcs_reg(&fbcs->cscr7, CONFIG_SYS_CS7_CTRL);
        out_be32(&fbcs->csmr7, CONFIG_SYS_CS7_MASK);
 #endif