mmc: mtk-sd: fix sclk cycles shift value

It turns out that the sclk cycles used by mt7620/mt7628 is the same as
other chips (20 bits, 1048576), not 65536.

This patch removes sclk_cycle_shift from dev_comp, and uses a macro with
a value 20 instead.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index 95dc9daee966f6bfd4252a5b79944be046fa7ffd..c6f697c7280a3d786f26e2a3abfc486bc01207e7 100644 (file)
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -166,6 +166,8 @@
 
 #define DEFAULT_CD_DEBOUNCE            8
 
+#define SCLK_CYCLES_SHIFT              20
+
 #define CMD_INTS_MASK  \
        (MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO)
 
@@ -256,7 +258,6 @@ struct msdc_top_regs {
 
 struct msdc_compatible {
        u8 clk_div_bits;
-       u8 sclk_cycle_shift;
        bool pad_tune0;
        bool async_fifo;
        bool data_tune;
@@ -722,7 +723,7 @@ static int msdc_ops_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 
 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
 {
-       u32 timeout, clk_ns, shift;
+       u32 timeout, clk_ns, shift = SCLK_CYCLES_SHIFT;
        u32 mode = 0;
 
        host->timeout_ns = ns;
@@ -731,7 +732,6 @@ static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
        if (host->sclk == 0) {
                timeout = 0;
        } else {
-               shift = host->dev_comp->sclk_cycle_shift;
                clk_ns = 1000000000UL / host->sclk;
                timeout = (ns + clk_ns - 1) / clk_ns + clks;
                /* unit is 1048576 sclk cycles */
@@ -1531,7 +1531,7 @@ static int msdc_drv_probe(struct udevice *dev)
 
        host->mmc = &plat->mmc;
        host->timeout_ns = 100000000;
-       host->timeout_clks = 3 * (1 << host->dev_comp->sclk_cycle_shift);
+       host->timeout_clks = 3 * (1 << SCLK_CYCLES_SHIFT);
 
 #ifdef CONFIG_PINCTRL
        pinctrl_select_state(dev, "default");
@@ -1615,7 +1615,6 @@ static const struct dm_mmc_ops msdc_ops = {
 
 static const struct msdc_compatible mt7620_compat = {
        .clk_div_bits = 8,
-       .sclk_cycle_shift = 16,
        .pad_tune0 = false,
        .async_fifo = false,
        .data_tune = false,
@@ -1635,7 +1634,6 @@ static const struct msdc_compatible mt7622_compat = {
 
 static const struct msdc_compatible mt7623_compat = {
        .clk_div_bits = 12,
-       .sclk_cycle_shift = 20,
        .pad_tune0 = true,
        .async_fifo = true,
        .data_tune = true,
@@ -1646,7 +1644,6 @@ static const struct msdc_compatible mt7623_compat = {
 
 static const struct msdc_compatible mt8512_compat = {
        .clk_div_bits = 12,
-       .sclk_cycle_shift = 20,
        .pad_tune0 = true,
        .async_fifo = true,
        .data_tune = true,
@@ -1656,7 +1653,6 @@ static const struct msdc_compatible mt8512_compat = {
 
 static const struct msdc_compatible mt8516_compat = {
        .clk_div_bits = 12,
-       .sclk_cycle_shift = 20,
        .pad_tune0 = true,
        .async_fifo = true,
        .data_tune = true,
@@ -1666,7 +1662,6 @@ static const struct msdc_compatible mt8516_compat = {
 
 static const struct msdc_compatible mt8183_compat = {
        .clk_div_bits = 12,
-       .sclk_cycle_shift = 20,
        .pad_tune0 = true,
        .async_fifo = true,
        .data_tune = true,