clk: renesas: Synchronize R-Car Gen3 tables with Linux 5.12

Synchronize R-Car Gen3 clock tables with Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12") .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index b13756496241308f320482f7036445e015d6645f..ca742502762849283f037ebf392474219910c032 100644 (file)
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -41,8 +41,8 @@ enum clk_ids {
        CLK_S2,
        CLK_S3,
        CLK_SDSRC,
-       CLK_RPCSRC,
        CLK_SSPSRC,
+       CLK_RPCSRC,
        CLK_RINT,
 
        /* Module Clocks */
@@ -69,13 +69,18 @@ static const struct cpg_core_clk r8a7795_core_clks[] = {
        DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),
        DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),
        DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),
-       DEF_FIXED(".rpcsrc",    CLK_RPCSRC,        CLK_PLL1,       2, 1),
+       DEF_BASE(".rpcsrc",     CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
+
+       DEF_BASE("rpc",         R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC,
+                CLK_RPCSRC),
+       DEF_BASE("rpcd2",       R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+                R8A7795_CLK_RPC),
 
        DEF_GEN3_OSC(".r",      CLK_RINT,          CLK_EXTAL,      32),
 
        /* Core Clock Outputs */
-       DEF_BASE("z",           R8A7795_CLK_Z,     CLK_TYPE_GEN3_Z, CLK_PLL0),
-       DEF_BASE("z2",          R8A7795_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2),
+       DEF_GEN3_Z("z",         R8A7795_CLK_Z,     CLK_TYPE_GEN3_Z,  CLK_PLL0, 2, 8),
+       DEF_GEN3_Z("z2",        R8A7795_CLK_Z2,    CLK_TYPE_GEN3_Z,  CLK_PLL2, 2, 0),
        DEF_FIXED("ztr",        R8A7795_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
        DEF_FIXED("ztrd2",      R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
        DEF_FIXED("zt",         R8A7795_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
@@ -102,8 +107,6 @@ static const struct cpg_core_clk r8a7795_core_clks[] = {
        DEF_GEN3_SD("sd2",      R8A7795_CLK_SD2,   CLK_SDSRC,     0x268),
        DEF_GEN3_SD("sd3",      R8A7795_CLK_SD3,   CLK_SDSRC,     0x26c),
 
-       DEF_GEN3_RPC("rpc",     R8A7795_CLK_RPC,   CLK_RPCSRC,    0x238),
-
        DEF_FIXED("cl",         R8A7795_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
        DEF_FIXED("cr",         R8A7795_CLK_CR,    CLK_PLL1_DIV4,  2, 1),
        DEF_FIXED("cp",         R8A7795_CLK_CP,    CLK_EXTAL,      2, 1),
@@ -132,14 +135,15 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
        DEF_MOD("msiof2",                209,   R8A7795_CLK_MSO),
        DEF_MOD("msiof1",                210,   R8A7795_CLK_MSO),
        DEF_MOD("msiof0",                211,   R8A7795_CLK_MSO),
-       DEF_MOD("sys-dmac2",             217,   R8A7795_CLK_S0D3),
-       DEF_MOD("sys-dmac1",             218,   R8A7795_CLK_S0D3),
+       DEF_MOD("sys-dmac2",             217,   R8A7795_CLK_S3D1),
+       DEF_MOD("sys-dmac1",             218,   R8A7795_CLK_S3D1),
        DEF_MOD("sys-dmac0",             219,   R8A7795_CLK_S0D3),
        DEF_MOD("sceg-pub",              229,   R8A7795_CLK_CR),
        DEF_MOD("cmt3",                  300,   R8A7795_CLK_R),
        DEF_MOD("cmt2",                  301,   R8A7795_CLK_R),
        DEF_MOD("cmt1",                  302,   R8A7795_CLK_R),
        DEF_MOD("cmt0",                  303,   R8A7795_CLK_R),
+       DEF_MOD("tpu0",                  304,   R8A7795_CLK_S3D4),
        DEF_MOD("scif2",                 310,   R8A7795_CLK_S3D4),
        DEF_MOD("sdif3",                 311,   R8A7795_CLK_SD3),
        DEF_MOD("sdif2",                 312,   R8A7795_CLK_SD2),
@@ -156,16 +160,16 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
        DEF_MOD("rwdt",                  402,   R8A7795_CLK_R),
        DEF_MOD("intc-ex",               407,   R8A7795_CLK_CP),
        DEF_MOD("intc-ap",               408,   R8A7795_CLK_S0D3),
-       DEF_MOD("audmac1",               501,   R8A7795_CLK_S0D3),
-       DEF_MOD("audmac0",               502,   R8A7795_CLK_S0D3),
-       DEF_MOD("drif7",                 508,   R8A7795_CLK_S3D2),
-       DEF_MOD("drif6",                 509,   R8A7795_CLK_S3D2),
-       DEF_MOD("drif5",                 510,   R8A7795_CLK_S3D2),
-       DEF_MOD("drif4",                 511,   R8A7795_CLK_S3D2),
-       DEF_MOD("drif3",                 512,   R8A7795_CLK_S3D2),
-       DEF_MOD("drif2",                 513,   R8A7795_CLK_S3D2),
-       DEF_MOD("drif1",                 514,   R8A7795_CLK_S3D2),
-       DEF_MOD("drif0",                 515,   R8A7795_CLK_S3D2),
+       DEF_MOD("audmac1",               501,   R8A7795_CLK_S1D2),
+       DEF_MOD("audmac0",               502,   R8A7795_CLK_S1D2),
+       DEF_MOD("drif31",                508,   R8A7795_CLK_S3D2),
+       DEF_MOD("drif30",                509,   R8A7795_CLK_S3D2),
+       DEF_MOD("drif21",                510,   R8A7795_CLK_S3D2),
+       DEF_MOD("drif20",                511,   R8A7795_CLK_S3D2),
+       DEF_MOD("drif11",                512,   R8A7795_CLK_S3D2),
+       DEF_MOD("drif10",                513,   R8A7795_CLK_S3D2),
+       DEF_MOD("drif01",                514,   R8A7795_CLK_S3D2),
+       DEF_MOD("drif00",                515,   R8A7795_CLK_S3D2),
        DEF_MOD("hscif4",                516,   R8A7795_CLK_S3D1),
        DEF_MOD("hscif3",                517,   R8A7795_CLK_S3D1),
        DEF_MOD("hscif2",                518,   R8A7795_CLK_S3D1),
@@ -197,12 +201,16 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
        DEF_MOD("vspi2",                 629,   R8A7795_CLK_S2D1), /* ES1.x */
        DEF_MOD("vspi1",                 630,   R8A7795_CLK_S0D1),
        DEF_MOD("vspi0",                 631,   R8A7795_CLK_S0D1),
-       DEF_MOD("ehci3",                 700,   R8A7795_CLK_S3D4),
-       DEF_MOD("ehci2",                 701,   R8A7795_CLK_S3D4),
-       DEF_MOD("ehci1",                 702,   R8A7795_CLK_S3D4),
-       DEF_MOD("ehci0",                 703,   R8A7795_CLK_S3D4),
-       DEF_MOD("hsusb",                 704,   R8A7795_CLK_S3D4),
-       DEF_MOD("hsusb3",                705,   R8A7795_CLK_S3D4),
+       DEF_MOD("ehci3",                 700,   R8A7795_CLK_S3D2),
+       DEF_MOD("ehci2",                 701,   R8A7795_CLK_S3D2),
+       DEF_MOD("ehci1",                 702,   R8A7795_CLK_S3D2),
+       DEF_MOD("ehci0",                 703,   R8A7795_CLK_S3D2),
+       DEF_MOD("hsusb",                 704,   R8A7795_CLK_S3D2),
+       DEF_MOD("hsusb3",                705,   R8A7795_CLK_S3D2),
+       DEF_MOD("cmm3",                  708,   R8A7795_CLK_S2D1),
+       DEF_MOD("cmm2",                  709,   R8A7795_CLK_S2D1),
+       DEF_MOD("cmm1",                  710,   R8A7795_CLK_S2D1),
+       DEF_MOD("cmm0",                  711,   R8A7795_CLK_S2D1),
        DEF_MOD("csi21",                 713,   R8A7795_CLK_CSI0), /* ES1.x */
        DEF_MOD("csi20",                 714,   R8A7795_CLK_CSI0),
        DEF_MOD("csi41",                 715,   R8A7795_CLK_CSI0),
@@ -239,7 +247,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
        DEF_MOD("can-fd",                914,   R8A7795_CLK_S3D2),
        DEF_MOD("can-if1",               915,   R8A7795_CLK_S3D4),
        DEF_MOD("can-if0",               916,   R8A7795_CLK_S3D4),
-       DEF_MOD("rpc",                   917,   R8A7795_CLK_RPC),
+       DEF_MOD("rpc-if",                917,   R8A7795_CLK_RPCD2),
        DEF_MOD("i2c6",                  918,   R8A7795_CLK_S0D6),
        DEF_MOD("i2c5",                  919,   R8A7795_CLK_S0D6),
        DEF_MOD("i2c-dvfs",              926,   R8A7795_CLK_CP),

diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 6745305a59c11eadcb24adf3411ab4184c14b704..2e9a8b6448eb106712a950ec7bcd35da8397d86d 100644 (file)
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -47,8 +47,8 @@ enum clk_ids {
        CLK_S2,
        CLK_S3,
        CLK_SDSRC,
-       CLK_RPCSRC,
        CLK_SSPSRC,
+       CLK_RPCSRC,
        CLK_RINT,
 
        /* Module Clocks */
@@ -75,13 +75,18 @@ static const struct cpg_core_clk r8a7796_core_clks[] = {
        DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  4, 1),
        DEF_FIXED(".s3",        CLK_S3,            CLK_PLL1_DIV2,  6, 1),
        DEF_FIXED(".sdsrc",     CLK_SDSRC,         CLK_PLL1_DIV2,  2, 1),
-       DEF_FIXED(".rpcsrc",    CLK_RPCSRC,        CLK_PLL1,       2, 1),
+       DEF_BASE(".rpcsrc",     CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
+
+       DEF_BASE("rpc",         R8A7796_CLK_RPC, CLK_TYPE_GEN3_RPC,
+                CLK_RPCSRC),
+       DEF_BASE("rpcd2",       R8A7796_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+                R8A7796_CLK_RPC),
 
        DEF_GEN3_OSC(".r",      CLK_RINT,          CLK_EXTAL,      32),
 
        /* Core Clock Outputs */
-       DEF_BASE("z",           R8A7796_CLK_Z,     CLK_TYPE_GEN3_Z, CLK_PLL0),
-       DEF_BASE("z2",          R8A7796_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2),
+       DEF_GEN3_Z("z",         R8A7796_CLK_Z,     CLK_TYPE_GEN3_Z,  CLK_PLL0, 2, 8),
+       DEF_GEN3_Z("z2",        R8A7796_CLK_Z2,    CLK_TYPE_GEN3_Z,  CLK_PLL2, 2, 0),
        DEF_FIXED("ztr",        R8A7796_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
        DEF_FIXED("ztrd2",      R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
        DEF_FIXED("zt",         R8A7796_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
@@ -108,9 +113,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] = {
        DEF_GEN3_SD("sd2",      R8A7796_CLK_SD2,   CLK_SDSRC,     0x268),
        DEF_GEN3_SD("sd3",      R8A7796_CLK_SD3,   CLK_SDSRC,     0x26c),
 
-       DEF_GEN3_RPC("rpc",     R8A7796_CLK_RPC,   CLK_RPCSRC,    0x238),
-
        DEF_FIXED("cl",         R8A7796_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
+       DEF_FIXED("cr",         R8A7796_CLK_CR,    CLK_PLL1_DIV4,  2, 1),
        DEF_FIXED("cp",         R8A7796_CLK_CP,    CLK_EXTAL,      2, 1),
        DEF_FIXED("cpex",       R8A7796_CLK_CPEX,  CLK_EXTAL,      2, 1),
 
@@ -126,6 +130,11 @@ static const struct cpg_core_clk r8a7796_core_clks[] = {
 
 static const struct mssr_mod_clk r8a7796_mod_clks[] = {
        DEF_MOD("fdp1-0",                119,   R8A7796_CLK_S0D1),
+       DEF_MOD("tmu4",                  121,   R8A7796_CLK_S0D6),
+       DEF_MOD("tmu3",                  122,   R8A7796_CLK_S3D2),
+       DEF_MOD("tmu2",                  123,   R8A7796_CLK_S3D2),
+       DEF_MOD("tmu1",                  124,   R8A7796_CLK_S3D2),
+       DEF_MOD("tmu0",                  125,   R8A7796_CLK_CP),
        DEF_MOD("scif5",                 202,   R8A7796_CLK_S3D4),
        DEF_MOD("scif4",                 203,   R8A7796_CLK_S3D4),
        DEF_MOD("scif3",                 204,   R8A7796_CLK_S3D4),
@@ -135,13 +144,15 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = {
        DEF_MOD("msiof2",                209,   R8A7796_CLK_MSO),
        DEF_MOD("msiof1",                210,   R8A7796_CLK_MSO),
        DEF_MOD("msiof0",                211,   R8A7796_CLK_MSO),
-       DEF_MOD("sys-dmac2",             217,   R8A7796_CLK_S0D3),
-       DEF_MOD("sys-dmac1",             218,   R8A7796_CLK_S0D3),
+       DEF_MOD("sys-dmac2",             217,   R8A7796_CLK_S3D1),
+       DEF_MOD("sys-dmac1",             218,   R8A7796_CLK_S3D1),
        DEF_MOD("sys-dmac0",             219,   R8A7796_CLK_S0D3),
+       DEF_MOD("sceg-pub",              229,   R8A7796_CLK_CR),
        DEF_MOD("cmt3",                  300,   R8A7796_CLK_R),
        DEF_MOD("cmt2",                  301,   R8A7796_CLK_R),
        DEF_MOD("cmt1",                  302,   R8A7796_CLK_R),
        DEF_MOD("cmt0",                  303,   R8A7796_CLK_R),
+       DEF_MOD("tpu0",                  304,   R8A7796_CLK_S3D4),
        DEF_MOD("scif2",                 310,   R8A7796_CLK_S3D4),
        DEF_MOD("sdif3",                 311,   R8A7796_CLK_SD3),
        DEF_MOD("sdif2",                 312,   R8A7796_CLK_SD2),
@@ -155,16 +166,16 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = {
        DEF_MOD("rwdt",                  402,   R8A7796_CLK_R),
        DEF_MOD("intc-ex",               407,   R8A7796_CLK_CP),
        DEF_MOD("intc-ap",               408,   R8A7796_CLK_S0D3),
-       DEF_MOD("audmac1",               501,   R8A7796_CLK_S0D3),
-       DEF_MOD("audmac0",               502,   R8A7796_CLK_S0D3),
-       DEF_MOD("drif7",                 508,   R8A7796_CLK_S3D2),
-       DEF_MOD("drif6",                 509,   R8A7796_CLK_S3D2),
-       DEF_MOD("drif5",                 510,   R8A7796_CLK_S3D2),
-       DEF_MOD("drif4",                 511,   R8A7796_CLK_S3D2),
-       DEF_MOD("drif3",                 512,   R8A7796_CLK_S3D2),
-       DEF_MOD("drif2",                 513,   R8A7796_CLK_S3D2),
-       DEF_MOD("drif1",                 514,   R8A7796_CLK_S3D2),
-       DEF_MOD("drif0",                 515,   R8A7796_CLK_S3D2),
+       DEF_MOD("audmac1",               501,   R8A7796_CLK_S1D2),
+       DEF_MOD("audmac0",               502,   R8A7796_CLK_S1D2),
+       DEF_MOD("drif31",                508,   R8A7796_CLK_S3D2),
+       DEF_MOD("drif30",                509,   R8A7796_CLK_S3D2),
+       DEF_MOD("drif21",                510,   R8A7796_CLK_S3D2),
+       DEF_MOD("drif20",                511,   R8A7796_CLK_S3D2),
+       DEF_MOD("drif11",                512,   R8A7796_CLK_S3D2),
+       DEF_MOD("drif10",                513,   R8A7796_CLK_S3D2),
+       DEF_MOD("drif01",                514,   R8A7796_CLK_S3D2),
+       DEF_MOD("drif00",                515,   R8A7796_CLK_S3D2),
        DEF_MOD("hscif4",                516,   R8A7796_CLK_S3D1),
        DEF_MOD("hscif3",                517,   R8A7796_CLK_S3D1),
        DEF_MOD("hscif2",                518,   R8A7796_CLK_S3D1),
@@ -185,9 +196,12 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = {
        DEF_MOD("vspd0",                 623,   R8A7796_CLK_S0D2),
        DEF_MOD("vspb",                  626,   R8A7796_CLK_S0D1),
        DEF_MOD("vspi0",                 631,   R8A7796_CLK_S0D1),
-       DEF_MOD("ehci1",                 702,   R8A7796_CLK_S3D4),
-       DEF_MOD("ehci0",                 703,   R8A7796_CLK_S3D4),
-       DEF_MOD("hsusb",                 704,   R8A7796_CLK_S3D4),
+       DEF_MOD("ehci1",                 702,   R8A7796_CLK_S3D2),
+       DEF_MOD("ehci0",                 703,   R8A7796_CLK_S3D2),
+       DEF_MOD("hsusb",                 704,   R8A7796_CLK_S3D2),
+       DEF_MOD("cmm2",                  709,   R8A7796_CLK_S2D1),
+       DEF_MOD("cmm1",                  710,   R8A7796_CLK_S2D1),
+       DEF_MOD("cmm0",                  711,   R8A7796_CLK_S2D1),
        DEF_MOD("csi20",                 714,   R8A7796_CLK_CSI0),
        DEF_MOD("csi40",                 716,   R8A7796_CLK_CSI0),
        DEF_MOD("du2",                   722,   R8A7796_CLK_S2D1),
@@ -217,7 +231,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = {
        DEF_MOD("can-fd",                914,   R8A7796_CLK_S3D2),
        DEF_MOD("can-if1",               915,   R8A7796_CLK_S3D4),
        DEF_MOD("can-if0",               916,   R8A7796_CLK_S3D4),
-       DEF_MOD("rpc",                   917,   R8A7796_CLK_RPC),
+       DEF_MOD("rpc-if",                917,   R8A7796_CLK_RPCD2),
        DEF_MOD("i2c6",                  918,   R8A7796_CLK_S0D6),
        DEF_MOD("i2c5",                  919,   R8A7796_CLK_S0D6),
        DEF_MOD("i2c-dvfs",              926,   R8A7796_CLK_CP),

diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index 8d792bceee394c97e5c009a5b2b3ffaee23403a5..a839ffa41f7335efb30c0db74db783fd82a1fe66 100644 (file)
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -41,8 +41,8 @@ enum clk_ids {
        CLK_S2,
        CLK_S3,
        CLK_SDSRC,
-       CLK_RPCSRC,
        CLK_SSPSRC,
+       CLK_RPCSRC,
        CLK_RINT,
 
        /* Module Clocks */
@@ -68,12 +68,17 @@ static const struct cpg_core_clk r8a77965_core_clks[] = {
        DEF_FIXED(".s2",        CLK_S2,                 CLK_PLL1_DIV2,  4, 1),
        DEF_FIXED(".s3",        CLK_S3,                 CLK_PLL1_DIV2,  6, 1),
        DEF_FIXED(".sdsrc",     CLK_SDSRC,              CLK_PLL1_DIV2,  2, 1),
-       DEF_FIXED(".rpcsrc",    CLK_RPCSRC,             CLK_PLL1,       2, 1),
+       DEF_BASE(".rpcsrc",     CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
+
+       DEF_BASE("rpc",         R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC,
+                CLK_RPCSRC),
+       DEF_BASE("rpcd2",       R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+                R8A77965_CLK_RPC),
 
        DEF_GEN3_OSC(".r",      CLK_RINT,               CLK_EXTAL,      32),
 
        /* Core Clock Outputs */
-       DEF_BASE("z",           R8A77965_CLK_Z,         CLK_TYPE_GEN3_Z, CLK_PLL0),
+       DEF_GEN3_Z("z",         R8A77965_CLK_Z,         CLK_TYPE_GEN3_Z,  CLK_PLL0, 2, 8),
        DEF_FIXED("ztr",        R8A77965_CLK_ZTR,       CLK_PLL1_DIV2,  6, 1),
        DEF_FIXED("ztrd2",      R8A77965_CLK_ZTRD2,     CLK_PLL1_DIV2,  12, 1),
        DEF_FIXED("zt",         R8A77965_CLK_ZT,        CLK_PLL1_DIV2,  4, 1),
@@ -100,9 +105,8 @@ static const struct cpg_core_clk r8a77965_core_clks[] = {
        DEF_GEN3_SD("sd2",      R8A77965_CLK_SD2,       CLK_SDSRC,      0x268),
        DEF_GEN3_SD("sd3",      R8A77965_CLK_SD3,       CLK_SDSRC,      0x26c),
 
-       DEF_GEN3_RPC("rpc",     R8A77965_CLK_RPC,       CLK_RPCSRC,     0x238),
-
-       DEF_FIXED("cl",         R8A77965_CLK_CL,        CLK_PLL1_DIV2,  48, 1),
+       DEF_FIXED("cl",         R8A77965_CLK_CL,        CLK_PLL1_DIV2, 48, 1),
+       DEF_FIXED("cr",         R8A77965_CLK_CR,        CLK_PLL1_DIV4,  2, 1),
        DEF_FIXED("cp",         R8A77965_CLK_CP,        CLK_EXTAL,      2, 1),
        DEF_FIXED("cpex",       R8A77965_CLK_CPEX,      CLK_EXTAL,      2, 1),
 
@@ -118,6 +122,11 @@ static const struct cpg_core_clk r8a77965_core_clks[] = {
 
 static const struct mssr_mod_clk r8a77965_mod_clks[] = {
        DEF_MOD("fdp1-0",               119,    R8A77965_CLK_S0D1),
+       DEF_MOD("tmu4",                 121,    R8A77965_CLK_S0D6),
+       DEF_MOD("tmu3",                 122,    R8A77965_CLK_S3D2),
+       DEF_MOD("tmu2",                 123,    R8A77965_CLK_S3D2),
+       DEF_MOD("tmu1",                 124,    R8A77965_CLK_S3D2),
+       DEF_MOD("tmu0",                 125,    R8A77965_CLK_CP),
        DEF_MOD("scif5",                202,    R8A77965_CLK_S3D4),
        DEF_MOD("scif4",                203,    R8A77965_CLK_S3D4),
        DEF_MOD("scif3",                204,    R8A77965_CLK_S3D4),
@@ -127,14 +136,16 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] = {
        DEF_MOD("msiof2",               209,    R8A77965_CLK_MSO),
        DEF_MOD("msiof1",               210,    R8A77965_CLK_MSO),
        DEF_MOD("msiof0",               211,    R8A77965_CLK_MSO),
-       DEF_MOD("sys-dmac2",            217,    R8A77965_CLK_S0D3),
-       DEF_MOD("sys-dmac1",            218,    R8A77965_CLK_S0D3),
+       DEF_MOD("sys-dmac2",            217,    R8A77965_CLK_S3D1),
+       DEF_MOD("sys-dmac1",            218,    R8A77965_CLK_S3D1),
        DEF_MOD("sys-dmac0",            219,    R8A77965_CLK_S0D3),
+       DEF_MOD("sceg-pub",             229,    R8A77965_CLK_CR),
 
        DEF_MOD("cmt3",                 300,    R8A77965_CLK_R),
        DEF_MOD("cmt2",                 301,    R8A77965_CLK_R),
        DEF_MOD("cmt1",                 302,    R8A77965_CLK_R),
        DEF_MOD("cmt0",                 303,    R8A77965_CLK_R),
+       DEF_MOD("tpu0",                 304,    R8A77965_CLK_S3D4),
        DEF_MOD("scif2",                310,    R8A77965_CLK_S3D4),
        DEF_MOD("sdif3",                311,    R8A77965_CLK_SD3),
        DEF_MOD("sdif2",                312,    R8A77965_CLK_SD2),
@@ -150,16 +161,16 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] = {
        DEF_MOD("intc-ex",              407,    R8A77965_CLK_CP),
        DEF_MOD("intc-ap",              408,    R8A77965_CLK_S0D3),
 
-       DEF_MOD("audmac1",              501,    R8A77965_CLK_S0D3),
-       DEF_MOD("audmac0",              502,    R8A77965_CLK_S0D3),
-       DEF_MOD("drif7",                508,    R8A77965_CLK_S3D2),
-       DEF_MOD("drif6",                509,    R8A77965_CLK_S3D2),
-       DEF_MOD("drif5",                510,    R8A77965_CLK_S3D2),
-       DEF_MOD("drif4",                511,    R8A77965_CLK_S3D2),
-       DEF_MOD("drif3",                512,    R8A77965_CLK_S3D2),
-       DEF_MOD("drif2",                513,    R8A77965_CLK_S3D2),
-       DEF_MOD("drif1",                514,    R8A77965_CLK_S3D2),
-       DEF_MOD("drif0",                515,    R8A77965_CLK_S3D2),
+       DEF_MOD("audmac1",              501,    R8A77965_CLK_S1D2),
+       DEF_MOD("audmac0",              502,    R8A77965_CLK_S1D2),
+       DEF_MOD("drif31",               508,    R8A77965_CLK_S3D2),
+       DEF_MOD("drif30",               509,    R8A77965_CLK_S3D2),
+       DEF_MOD("drif21",               510,    R8A77965_CLK_S3D2),
+       DEF_MOD("drif20",               511,    R8A77965_CLK_S3D2),
+       DEF_MOD("drif11",               512,    R8A77965_CLK_S3D2),
+       DEF_MOD("drif10",               513,    R8A77965_CLK_S3D2),
+       DEF_MOD("drif01",               514,    R8A77965_CLK_S3D2),
+       DEF_MOD("drif00",               515,    R8A77965_CLK_S3D2),
        DEF_MOD("hscif4",               516,    R8A77965_CLK_S3D1),
        DEF_MOD("hscif3",               517,    R8A77965_CLK_S3D1),
        DEF_MOD("hscif2",               518,    R8A77965_CLK_S3D1),
@@ -179,9 +190,12 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] = {
        DEF_MOD("vspb",                 626,    R8A77965_CLK_S0D1),
        DEF_MOD("vspi0",                631,    R8A77965_CLK_S0D1),
 
-       DEF_MOD("ehci1",                702,    R8A77965_CLK_S3D4),
-       DEF_MOD("ehci0",                703,    R8A77965_CLK_S3D4),
-       DEF_MOD("hsusb",                704,    R8A77965_CLK_S3D4),
+       DEF_MOD("ehci1",                702,    R8A77965_CLK_S3D2),
+       DEF_MOD("ehci0",                703,    R8A77965_CLK_S3D2),
+       DEF_MOD("hsusb",                704,    R8A77965_CLK_S3D2),
+       DEF_MOD("cmm3",                 708,    R8A77965_CLK_S2D1),
+       DEF_MOD("cmm1",                 710,    R8A77965_CLK_S2D1),
+       DEF_MOD("cmm0",                 711,    R8A77965_CLK_S2D1),
        DEF_MOD("csi20",                714,    R8A77965_CLK_CSI0),
        DEF_MOD("csi40",                716,    R8A77965_CLK_CSI0),
        DEF_MOD("du3",                  721,    R8A77965_CLK_S2D1),
@@ -214,7 +228,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] = {
        DEF_MOD("can-fd",               914,    R8A77965_CLK_S3D2),
        DEF_MOD("can-if1",              915,    R8A77965_CLK_S3D4),
        DEF_MOD("can-if0",              916,    R8A77965_CLK_S3D4),
-       DEF_MOD("rpc",                  917,    R8A77965_CLK_RPC),
+       DEF_MOD("rpc-if",               917,    R8A77965_CLK_RPCD2),
        DEF_MOD("i2c6",                 918,    R8A77965_CLK_S0D6),
        DEF_MOD("i2c5",                 919,    R8A77965_CLK_S0D6),
        DEF_MOD("i2c-dvfs",             926,    R8A77965_CLK_CP),

diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c b/drivers/clk/renesas/r8a77970-cpg-mssr.c
index b2b32be9465c5e86667a6111a88c2fb8521c0955..3b84c658f7c2ae83c6a15210bd8235609ca1217c 100644 (file)
--- a/drivers/clk/renesas/r8a77970-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c
@@ -20,6 +20,13 @@
 #include "renesas-cpg-mssr.h"
 #include "rcar-gen3-cpg.h"
 
+#define CPG_SD0CKCR            0x0074
+
+enum r8a77970_clk_types {
+       CLK_TYPE_R8A77970_SD0H = CLK_TYPE_GEN3_SOC_BASE,
+       CLK_TYPE_R8A77970_SD0,
+};
+
 enum clk_ids {
        /* Core Clock Outputs exported to DT */
        LAST_DT_CORE_CLK = R8A77970_CLK_OSC,
@@ -32,24 +39,9 @@ enum clk_ids {
        CLK_MAIN,
        CLK_PLL0,
        CLK_PLL1,
-       CLK_PLL2,
        CLK_PLL3,
-       CLK_PLL4,
        CLK_PLL1_DIV2,
        CLK_PLL1_DIV4,
-       CLK_PLL0D2,
-       CLK_PLL0D3,
-       CLK_PLL0D5,
-       CLK_PLL1D2,
-       CLK_PE,
-       CLK_S0,
-       CLK_S1,
-       CLK_S2,
-       CLK_S3,
-       CLK_SDSRC,
-       CLK_RPCSRC,
-       CLK_SSPSRC,
-       CLK_RINT,
 
        /* Module Clocks */
        MOD_CLK_BASE
@@ -57,67 +49,80 @@ enum clk_ids {
 
 static const struct cpg_core_clk r8a77970_core_clks[] = {
        /* External Clock Inputs */
-       DEF_INPUT("extal",  CLK_EXTAL),
-       DEF_INPUT("extalr", CLK_EXTALR),
+       DEF_INPUT("extal",      CLK_EXTAL),
+       DEF_INPUT("extalr",     CLK_EXTALR),
 
        /* Internal Core Clocks */
-       DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
-       DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
-       DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
-       DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
+       DEF_BASE(".main",       CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+       DEF_BASE(".pll0",       CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
+       DEF_BASE(".pll1",       CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+       DEF_BASE(".pll3",       CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
 
-       DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,     CLK_PLL1,       2, 1),
-       DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4,     CLK_PLL1_DIV2,  2, 1),
-       DEF_FIXED(".s1",        CLK_S1,            CLK_PLL1_DIV2,  4, 1),
-       DEF_FIXED(".s2",        CLK_S2,            CLK_PLL1_DIV2,  6, 1),
-       DEF_FIXED(".rpcsrc",    CLK_RPCSRC,        CLK_PLL1,       2, 1),
+       DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2,  CLK_PLL1,       2, 1),
+       DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4,  CLK_PLL1_DIV2,  2, 1),
 
        /* Core Clock Outputs */
-       DEF_BASE("z2",          R8A77970_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL1_DIV4),
-       DEF_FIXED("ztr",        R8A77970_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
-       DEF_FIXED("ztrd2",      R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
-       DEF_FIXED("zt",         R8A77970_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
-       DEF_FIXED("zx",         R8A77970_CLK_ZX,    CLK_PLL1_DIV2,  3, 1),
-       DEF_FIXED("s1d1",       R8A77970_CLK_S1D1,  CLK_S1,         1, 1),
-       DEF_FIXED("s1d2",       R8A77970_CLK_S1D2,  CLK_S1,         2, 1),
-       DEF_FIXED("s1d4",       R8A77970_CLK_S1D4,  CLK_S1,         4, 1),
-       DEF_FIXED("s2d1",       R8A77970_CLK_S2D1,  CLK_S2,         1, 1),
-       DEF_FIXED("s2d2",       R8A77970_CLK_S2D2,  CLK_S2,         2, 1),
-       DEF_FIXED("s2d4",       R8A77970_CLK_S2D4,  CLK_S2,         4, 1),
-
-       DEF_GEN3_SD("sd0",      R8A77970_CLK_SD0,   CLK_PLL1_DIV4, 0x0074),
-
-       DEF_GEN3_RPC("rpc",     R8A77970_CLK_RPC,   CLK_RPCSRC,    0x238),
-
-       DEF_FIXED("cl",         R8A77970_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
-       DEF_FIXED("cp",         R8A77970_CLK_CP,    CLK_EXTAL,      2, 1),
-
-       /* NOTE: HDMI, CSI, CAN etc. clock are missing */
-
-       DEF_BASE("r",           R8A77970_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
+       DEF_FIXED("ztr",        R8A77970_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),
+       DEF_FIXED("ztrd2",      R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
+       DEF_FIXED("zt",         R8A77970_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
+       DEF_FIXED("zx",         R8A77970_CLK_ZX,    CLK_PLL1_DIV2,  3, 1),
+       DEF_FIXED("s1d1",       R8A77970_CLK_S1D1,  CLK_PLL1_DIV2,  4, 1),
+       DEF_FIXED("s1d2",       R8A77970_CLK_S1D2,  CLK_PLL1_DIV2,  8, 1),
+       DEF_FIXED("s1d4",       R8A77970_CLK_S1D4,  CLK_PLL1_DIV2, 16, 1),
+       DEF_FIXED("s2d1",       R8A77970_CLK_S2D1,  CLK_PLL1_DIV2,  6, 1),
+       DEF_FIXED("s2d2",       R8A77970_CLK_S2D2,  CLK_PLL1_DIV2, 12, 1),
+       DEF_FIXED("s2d4",       R8A77970_CLK_S2D4,  CLK_PLL1_DIV2, 24, 1),
+
+       DEF_BASE("sd0h", R8A77970_CLK_SD0H, CLK_TYPE_R8A77970_SD0H,
+                CLK_PLL1_DIV2),
+       DEF_BASE("sd0", R8A77970_CLK_SD0, CLK_TYPE_R8A77970_SD0, CLK_PLL1_DIV2),
+
+       DEF_FIXED("rpc",        R8A77970_CLK_RPC,   CLK_PLL1_DIV2,  5, 1),
+       DEF_FIXED("rpcd2",      R8A77970_CLK_RPCD2, CLK_PLL1_DIV2, 10, 1),
+
+       DEF_FIXED("cl",         R8A77970_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
+       DEF_FIXED("cp",         R8A77970_CLK_CP,    CLK_EXTAL,      2, 1),
+       DEF_FIXED("cpex",       R8A77970_CLK_CPEX,  CLK_EXTAL,      2, 1),
+
+       DEF_DIV6P1("canfd",     R8A77970_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
+       DEF_DIV6P1("mso",       R8A77970_CLK_MSO,   CLK_PLL1_DIV4, 0x014),
+       DEF_DIV6P1("csi0",      R8A77970_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),
+
+       DEF_FIXED("osc",        R8A77970_CLK_OSC,   CLK_PLL1_DIV2, 12*1024, 1),
+       DEF_FIXED("r",          R8A77970_CLK_R,     CLK_EXTALR,    1, 1),
 };
 
 static const struct mssr_mod_clk r8a77970_mod_clks[] = {
+       DEF_MOD("tmu4",                  121,   R8A77970_CLK_S2D2),
+       DEF_MOD("tmu3",                  122,   R8A77970_CLK_S2D2),
+       DEF_MOD("tmu2",                  123,   R8A77970_CLK_S2D2),
+       DEF_MOD("tmu1",                  124,   R8A77970_CLK_S2D2),
+       DEF_MOD("tmu0",                  125,   R8A77970_CLK_CP),
        DEF_MOD("ivcp1e",                127,   R8A77970_CLK_S2D1),
-       DEF_MOD("scif4",                 203,   R8A77970_CLK_S2D4),     /* @@ H3=S3D4 */
-       DEF_MOD("scif3",                 204,   R8A77970_CLK_S2D4),     /* @@ H3=S3D4 */
-       DEF_MOD("scif1",                 206,   R8A77970_CLK_S2D4),     /* @@ H3=S3D4 */
-       DEF_MOD("scif0",                 207,   R8A77970_CLK_S2D4),     /* @@ H3=S3D4 */
+       DEF_MOD("scif4",                 203,   R8A77970_CLK_S2D4),
+       DEF_MOD("scif3",                 204,   R8A77970_CLK_S2D4),
+       DEF_MOD("scif1",                 206,   R8A77970_CLK_S2D4),
+       DEF_MOD("scif0",                 207,   R8A77970_CLK_S2D4),
        DEF_MOD("msiof3",                208,   R8A77970_CLK_MSO),
        DEF_MOD("msiof2",                209,   R8A77970_CLK_MSO),
        DEF_MOD("msiof1",                210,   R8A77970_CLK_MSO),
        DEF_MOD("msiof0",                211,   R8A77970_CLK_MSO),
-       DEF_MOD("mfis",                  213,   R8A77970_CLK_S2D2),     /* @@ H3=S3D2 */
-       DEF_MOD("sys-dmac2",     217,   R8A77970_CLK_S2D1),     /* @@ H3=S3D1 */
-       DEF_MOD("sys-dmac1",     218,   R8A77970_CLK_S2D1),     /* @@ H3=S3D1 */
-       DEF_MOD("sdif",                  314,   R8A77970_CLK_SD0),
-       DEF_MOD("rwdt0",                 402,   R8A77970_CLK_R),
+       DEF_MOD("mfis",                  213,   R8A77970_CLK_S2D2),
+       DEF_MOD("sys-dmac2",             217,   R8A77970_CLK_S2D1),
+       DEF_MOD("sys-dmac1",             218,   R8A77970_CLK_S2D1),
+       DEF_MOD("cmt3",                  300,   R8A77970_CLK_R),
+       DEF_MOD("cmt2",                  301,   R8A77970_CLK_R),
+       DEF_MOD("cmt1",                  302,   R8A77970_CLK_R),
+       DEF_MOD("cmt0",                  303,   R8A77970_CLK_R),
+       DEF_MOD("tpu0",                  304,   R8A77970_CLK_S2D4),
+       DEF_MOD("sd-if",                 314,   R8A77970_CLK_SD0),
+       DEF_MOD("rwdt",                  402,   R8A77970_CLK_R),
        DEF_MOD("intc-ex",               407,   R8A77970_CLK_CP),
-       DEF_MOD("intc-ap",               408,   R8A77970_CLK_S2D1),     /* @@ H3=S3D1 */
-       DEF_MOD("hscif3",                517,   R8A77970_CLK_S2D1),     /* @@ H3=S3D1 */
-       DEF_MOD("hscif2",                518,   R8A77970_CLK_S2D1),     /* @@ H3=S3D1 */
-       DEF_MOD("hscif1",                519,   R8A77970_CLK_S2D1),     /* @@ H3=S3D1 */
-       DEF_MOD("hscif0",                520,   R8A77970_CLK_S2D1),     /* @@ H3=S3D1 */
+       DEF_MOD("intc-ap",               408,   R8A77970_CLK_S2D1),
+       DEF_MOD("hscif3",                517,   R8A77970_CLK_S2D1),
+       DEF_MOD("hscif2",                518,   R8A77970_CLK_S2D1),
+       DEF_MOD("hscif1",                519,   R8A77970_CLK_S2D1),
+       DEF_MOD("hscif0",                520,   R8A77970_CLK_S2D1),
        DEF_MOD("thermal",               522,   R8A77970_CLK_CP),
        DEF_MOD("pwm",                   523,   R8A77970_CLK_S2D4),
        DEF_MOD("fcpvd0",                603,   R8A77970_CLK_S2D1),
@@ -130,7 +135,6 @@ static const struct mssr_mod_clk r8a77970_mod_clks[] = {
        DEF_MOD("vin1",                  810,   R8A77970_CLK_S2D1),
        DEF_MOD("vin0",                  811,   R8A77970_CLK_S2D1),
        DEF_MOD("etheravb",              812,   R8A77970_CLK_S2D2),
-       DEF_MOD("isp",                   817,   R8A77970_CLK_S2D1),
        DEF_MOD("gpio5",                 907,   R8A77970_CLK_CP),
        DEF_MOD("gpio4",                 908,   R8A77970_CLK_CP),
        DEF_MOD("gpio3",                 909,   R8A77970_CLK_CP),
@@ -138,7 +142,7 @@ static const struct mssr_mod_clk r8a77970_mod_clks[] = {
        DEF_MOD("gpio1",                 911,   R8A77970_CLK_CP),
        DEF_MOD("gpio0",                 912,   R8A77970_CLK_CP),
        DEF_MOD("can-fd",                914,   R8A77970_CLK_S2D2),
-       DEF_MOD("rpc",                   917,   R8A77970_CLK_RPC),
+       DEF_MOD("rpc-if",                917,   R8A77970_CLK_RPC),
        DEF_MOD("i2c4",                  927,   R8A77970_CLK_S2D2),
        DEF_MOD("i2c3",                  928,   R8A77970_CLK_S2D2),
        DEF_MOD("i2c2",                  929,   R8A77970_CLK_S2D2),

diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index e983296b3a255d68348ce869e2541175bef9e34c..504dc871d1dc8d4e1dea1a21308a5a95a8298e2c 100644 (file)
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -44,7 +44,6 @@ enum clk_ids {
        CLK_S2,
        CLK_S3,
        CLK_SDSRC,
-       CLK_RPCSRC,
        CLK_RINT,
        CLK_OCO,
 
@@ -74,7 +73,6 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
        DEF_FIXED(".s2",       CLK_S2,             CLK_PLL1,       4, 1),
        DEF_FIXED(".s3",       CLK_S3,             CLK_PLL1,       6, 1),
        DEF_FIXED(".sdsrc",    CLK_SDSRC,          CLK_PLL1,       2, 1),
-       DEF_FIXED(".rpcsrc",   CLK_RPCSRC,         CLK_PLL1,       2, 1),
 
        DEF_DIV6_RO(".r",      CLK_RINT,           CLK_EXTAL, CPG_RCKCR, 32),
 
@@ -83,6 +81,7 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
        /* Core Clock Outputs */
        DEF_FIXED("za2",       R8A77990_CLK_ZA2,   CLK_PLL0D24,    1, 1),
        DEF_FIXED("za8",       R8A77990_CLK_ZA8,   CLK_PLL0D8,     1, 1),
+       DEF_GEN3_Z("z2",       R8A77990_CLK_Z2,    CLK_TYPE_GEN3_Z, CLK_PLL0, 4, 8),
        DEF_FIXED("ztr",       R8A77990_CLK_ZTR,   CLK_PLL1,       6, 1),
        DEF_FIXED("zt",        R8A77990_CLK_ZT,    CLK_PLL1,       4, 1),
        DEF_FIXED("zx",        R8A77990_CLK_ZX,    CLK_PLL1,       3, 1),
@@ -105,9 +104,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
        DEF_GEN3_SD("sd1",     R8A77990_CLK_SD1,   CLK_SDSRC,     0x0078),
        DEF_GEN3_SD("sd3",     R8A77990_CLK_SD3,   CLK_SDSRC,     0x026c),
 
-       DEF_GEN3_RPC("rpc",    R8A77990_CLK_RPC,   CLK_RPCSRC,    0x238),
-
        DEF_FIXED("cl",        R8A77990_CLK_CL,    CLK_PLL1,      48, 1),
+       DEF_FIXED("cr",        R8A77990_CLK_CR,    CLK_PLL1D2,     2, 1),
        DEF_FIXED("cp",        R8A77990_CLK_CP,    CLK_EXTAL,      2, 1),
        DEF_FIXED("cpex",      R8A77990_CLK_CPEX,  CLK_EXTAL,      4, 1),
 
@@ -126,6 +124,11 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
 };
 
 static const struct mssr_mod_clk r8a77990_mod_clks[] = {
+       DEF_MOD("tmu4",                  121,   R8A77990_CLK_S0D6C),
+       DEF_MOD("tmu3",                  122,   R8A77990_CLK_S3D2C),
+       DEF_MOD("tmu2",                  123,   R8A77990_CLK_S3D2C),
+       DEF_MOD("tmu1",                  124,   R8A77990_CLK_S3D2C),
+       DEF_MOD("tmu0",                  125,   R8A77990_CLK_CP),
        DEF_MOD("scif5",                 202,   R8A77990_CLK_S3D4C),
        DEF_MOD("scif4",                 203,   R8A77990_CLK_S3D4C),
        DEF_MOD("scif3",                 204,   R8A77990_CLK_S3D4C),
@@ -138,6 +141,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
        DEF_MOD("sys-dmac2",             217,   R8A77990_CLK_S3D1),
        DEF_MOD("sys-dmac1",             218,   R8A77990_CLK_S3D1),
        DEF_MOD("sys-dmac0",             219,   R8A77990_CLK_S3D1),
+       DEF_MOD("sceg-pub",              229,   R8A77990_CLK_CR),
 
        DEF_MOD("cmt3",                  300,   R8A77990_CLK_R),
        DEF_MOD("cmt2",                  301,   R8A77990_CLK_R),
@@ -156,15 +160,15 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
        DEF_MOD("intc-ex",               407,   R8A77990_CLK_CP),
        DEF_MOD("intc-ap",               408,   R8A77990_CLK_S0D3),
 
-       DEF_MOD("audmac0",               502,   R8A77990_CLK_S3D4),
-       DEF_MOD("drif7",                 508,   R8A77990_CLK_S3D2),
-       DEF_MOD("drif6",                 509,   R8A77990_CLK_S3D2),
-       DEF_MOD("drif5",                 510,   R8A77990_CLK_S3D2),
-       DEF_MOD("drif4",                 511,   R8A77990_CLK_S3D2),
-       DEF_MOD("drif3",                 512,   R8A77990_CLK_S3D2),
-       DEF_MOD("drif2",                 513,   R8A77990_CLK_S3D2),
-       DEF_MOD("drif1",                 514,   R8A77990_CLK_S3D2),
-       DEF_MOD("drif0",                 515,   R8A77990_CLK_S3D2),
+       DEF_MOD("audmac0",               502,   R8A77990_CLK_S1D2),
+       DEF_MOD("drif31",                508,   R8A77990_CLK_S3D2),
+       DEF_MOD("drif30",                509,   R8A77990_CLK_S3D2),
+       DEF_MOD("drif21",                510,   R8A77990_CLK_S3D2),
+       DEF_MOD("drif20",                511,   R8A77990_CLK_S3D2),
+       DEF_MOD("drif11",                512,   R8A77990_CLK_S3D2),
+       DEF_MOD("drif10",                513,   R8A77990_CLK_S3D2),
+       DEF_MOD("drif01",                514,   R8A77990_CLK_S3D2),
+       DEF_MOD("drif00",                515,   R8A77990_CLK_S3D2),
        DEF_MOD("hscif4",                516,   R8A77990_CLK_S3D1C),
        DEF_MOD("hscif3",                517,   R8A77990_CLK_S3D1C),
        DEF_MOD("hscif2",                518,   R8A77990_CLK_S3D1C),
@@ -184,8 +188,10 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
        DEF_MOD("vspb",                  626,   R8A77990_CLK_S0D1),
        DEF_MOD("vspi0",                 631,   R8A77990_CLK_S0D1),
 
-       DEF_MOD("ehci0",                 703,   R8A77990_CLK_S3D4),
-       DEF_MOD("hsusb",                 704,   R8A77990_CLK_S3D4),
+       DEF_MOD("ehci0",                 703,   R8A77990_CLK_S3D2),
+       DEF_MOD("hsusb",                 704,   R8A77990_CLK_S3D2),
+       DEF_MOD("cmm1",                  710,   R8A77990_CLK_S1D1),
+       DEF_MOD("cmm0",                  711,   R8A77990_CLK_S1D1),
        DEF_MOD("csi40",                 716,   R8A77990_CLK_CSI0),
        DEF_MOD("du1",                   723,   R8A77990_CLK_S1D1),
        DEF_MOD("du0",                   724,   R8A77990_CLK_S1D1),
@@ -205,7 +211,6 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
        DEF_MOD("can-fd",                914,   R8A77990_CLK_S3D2),
        DEF_MOD("can-if1",               915,   R8A77990_CLK_S3D4),
        DEF_MOD("can-if0",               916,   R8A77990_CLK_S3D4),
-       DEF_MOD("rpc",                   917,   R8A77990_CLK_RPC),
        DEF_MOD("i2c6",                  918,   R8A77990_CLK_S3D2),
        DEF_MOD("i2c5",                  919,   R8A77990_CLK_S3D2),
        DEF_MOD("i2c-dvfs",              926,   R8A77990_CLK_CP),

diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
index fb1df6d10e49593022a37f47050418e52b9a2d38..58dc295d6a0dedf41ed3abb2bb47be9f2476e500 100644 (file)
--- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -42,7 +42,6 @@ enum clk_ids {
        CLK_S2,
        CLK_S3,
        CLK_SDSRC,
-       CLK_RPCSRC,
        CLK_RINT,
        CLK_OCO,
 
@@ -70,7 +69,6 @@ static const struct cpg_core_clk r8a77995_core_clks[] = {
        DEF_FIXED(".s2",       CLK_S2,             CLK_PLL1,       4, 1),
        DEF_FIXED(".s3",       CLK_S3,             CLK_PLL1,       6, 1),
        DEF_FIXED(".sdsrc",    CLK_SDSRC,          CLK_PLL1,       2, 1),
-       DEF_FIXED(".rpcsrc",   CLK_RPCSRC,         CLK_PLL1,       2, 1),
 
        DEF_DIV6_RO(".r",      CLK_RINT,           CLK_EXTAL, CPG_RCKCR, 32),
 
@@ -93,13 +91,12 @@ static const struct cpg_core_clk r8a77995_core_clks[] = {
        DEF_FIXED("s3d4",      R8A77995_CLK_S3D4,  CLK_S3,         4, 1),
 
        DEF_FIXED("cl",        R8A77995_CLK_CL,    CLK_PLL1,      48, 1),
+       DEF_FIXED("cr",        R8A77995_CLK_CR,    CLK_PLL1D2,     2, 1),
        DEF_FIXED("cp",        R8A77995_CLK_CP,    CLK_EXTAL,      2, 1),
        DEF_FIXED("cpex",      R8A77995_CLK_CPEX,  CLK_EXTAL,      4, 1),
 
        DEF_DIV6_RO("osc",     R8A77995_CLK_OSC,   CLK_EXTAL, CPG_RCKCR,  8),
 
-       DEF_GEN3_RPC("rpc",    R8A77995_CLK_RPC,   CLK_RPCSRC,    0x238),
-
        DEF_GEN3_PE("s1d4c",   R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
        DEF_GEN3_PE("s3d1c",   R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
        DEF_GEN3_PE("s3d2c",   R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
@@ -114,6 +111,11 @@ static const struct cpg_core_clk r8a77995_core_clks[] = {
 };
 
 static const struct mssr_mod_clk r8a77995_mod_clks[] = {
+       DEF_MOD("tmu4",                  121,   R8A77995_CLK_S1D4C),
+       DEF_MOD("tmu3",                  122,   R8A77995_CLK_S3D2C),
+       DEF_MOD("tmu2",                  123,   R8A77995_CLK_S3D2C),
+       DEF_MOD("tmu1",                  124,   R8A77995_CLK_S3D2C),
+       DEF_MOD("tmu0",                  125,   R8A77995_CLK_CP),
        DEF_MOD("scif5",                 202,   R8A77995_CLK_S3D4C),
        DEF_MOD("scif4",                 203,   R8A77995_CLK_S3D4C),
        DEF_MOD("scif3",                 204,   R8A77995_CLK_S3D4C),
@@ -126,6 +128,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = {
        DEF_MOD("sys-dmac2",             217,   R8A77995_CLK_S3D1),
        DEF_MOD("sys-dmac1",             218,   R8A77995_CLK_S3D1),
        DEF_MOD("sys-dmac0",             219,   R8A77995_CLK_S3D1),
+       DEF_MOD("sceg-pub",              229,   R8A77995_CLK_CR),
        DEF_MOD("cmt3",                  300,   R8A77995_CLK_R),
        DEF_MOD("cmt2",                  301,   R8A77995_CLK_R),
        DEF_MOD("cmt1",                  302,   R8A77995_CLK_R),
@@ -137,7 +140,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = {
        DEF_MOD("rwdt",                  402,   R8A77995_CLK_R),
        DEF_MOD("intc-ex",               407,   R8A77995_CLK_CP),
        DEF_MOD("intc-ap",               408,   R8A77995_CLK_S1D2),
-       DEF_MOD("audmac0",               502,   R8A77995_CLK_S3D1),
+       DEF_MOD("audmac0",               502,   R8A77995_CLK_S1D2),
        DEF_MOD("hscif3",                517,   R8A77995_CLK_S3D1C),
        DEF_MOD("hscif0",                520,   R8A77995_CLK_S3D1C),
        DEF_MOD("thermal",               522,   R8A77995_CLK_CP),
@@ -150,6 +153,8 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = {
        DEF_MOD("vspbs",                 627,   R8A77995_CLK_S0D1),
        DEF_MOD("ehci0",                 703,   R8A77995_CLK_S3D2),
        DEF_MOD("hsusb",                 704,   R8A77995_CLK_S3D2),
+       DEF_MOD("cmm1",                  710,   R8A77995_CLK_S1D1),
+       DEF_MOD("cmm0",                  711,   R8A77995_CLK_S1D1),
        DEF_MOD("du1",                   723,   R8A77995_CLK_S1D1),
        DEF_MOD("du0",                   724,   R8A77995_CLK_S1D1),
        DEF_MOD("lvds",                  727,   R8A77995_CLK_S2D1),
@@ -166,7 +171,6 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = {
        DEF_MOD("can-fd",                914,   R8A77995_CLK_S3D2),
        DEF_MOD("can-if1",               915,   R8A77995_CLK_S3D4),
        DEF_MOD("can-if0",               916,   R8A77995_CLK_S3D4),
-       DEF_MOD("rpc",                   917,   R8A77995_CLK_RPC),
        DEF_MOD("i2c3",                  928,   R8A77995_CLK_S3D2),
        DEF_MOD("i2c2",                  929,   R8A77995_CLK_S3D2),
        DEF_MOD("i2c1",                  930,   R8A77995_CLK_S3D2),

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index 3beae7d82509b9071bf7dc6e2eadbff43a1dac20..8265c96cf62f4ca10accfd6fd2835e9fc852304f 100644 (file)
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -1,11 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * R-Car Gen3 Clock Pulse Generator
  *
- * Copyright (C) 2015-2016 Glider bvba
+ * Copyright (C) 2015-2018 Glider bvba
+ * Copyright (C) 2018 Renesas Electronics Corp.
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
  */
 
 #ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
@@ -22,10 +21,10 @@ enum rcar_gen3_clk_types {
        CLK_TYPE_GEN3_R,
        CLK_TYPE_GEN3_MDSEL,    /* Select parent/divider using mode pin */
        CLK_TYPE_GEN3_Z,
-       CLK_TYPE_GEN3_Z2,
        CLK_TYPE_GEN3_OSC,      /* OSC EXTAL predivider and fixed divider */
        CLK_TYPE_GEN3_RCKSEL,   /* Select parent/divider using RCKCR.CKSEL */
        CLK_TYPE_GEN3_RPCSRC,
+       CLK_TYPE_GEN3_E3_RPCSRC,
        CLK_TYPE_GEN3_RPC,
        CLK_TYPE_GEN3_RPCD2,
 
@@ -36,9 +35,6 @@ enum rcar_gen3_clk_types {
 #define DEF_GEN3_SD(_name, _id, _parent, _offset)      \
        DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
 
-#define DEF_GEN3_RPC(_name, _id, _parent, _offset)     \
-       DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
-
 #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
        DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL,       \
                 (_parent0) << 16 | (_parent1),         \
@@ -59,6 +55,10 @@ enum rcar_gen3_clk_types {
 #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset)  \
        DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
 
+#define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1)    \
+       DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC,   \
+                (_parent0) << 16 | (_parent1), .div = 8)
+
 struct rcar_gen3_cpg_pll_config {
        u8 extal_div;
        u8 pll1_mult;