void sdram_init(void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
- volatile lbus8349_t *lbc= &immap->lbus;
+ volatile lbus83xx_t *lbc= &immap->lbus;
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
puts("\n SDRAM on Local Bus: ");
void ecc_print_status(void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
- volatile ddr8349_t *ddr = &immap->ddr;
+ volatile ddr83xx_t *ddr = &immap->ddr;
printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
- volatile ddr8349_t *ddr = &immap->ddr;
+ volatile ddr83xx_t *ddr = &immap->ddr;
volatile u32 val;
u64 *addr, count, val64;
register u64 *i;
/*
- * Copyright 2004 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
void dma_init(void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
- volatile dma8349_t *dma = &immap->dma;
+ volatile dma83xx_t *dma = &immap->dma;
volatile u32 status = swab32(dma->dmasr0);
volatile u32 dmamr0 = swab32(dma->dmamr0);
uint dma_check(void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
- volatile dma8349_t *dma = &immap->dma;
+ volatile dma83xx_t *dma = &immap->dma;
volatile u32 status = swab32(dma->dmasr0);
volatile u32 byte_count = swab32(dma->dmabcr0);
int dma_xfer(void *dest, u32 count, void *src)
{
volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
- volatile dma8349_t *dma = &immap->dma;
+ volatile dma83xx_t *dma = &immap->dma;
volatile u32 dmamr0;
/* initialize DMASARn, DMADAR and DMAABCRn */
/*
+ * (C) Copyright 2006 Freescale Semiconductor, Inc.
+ *
* (C) Copyright 2003,Motorola Inc.
* Xianghua Xiao <x.xiao@motorola.com>
* Adapted for Motorola 85xx chip.
*
* 20050101: Eran Liberty (liberty@freescale.com)
* Initial file creating (porting from 85XX & 8260)
+ * 20060601: Dave Liu (daveliu@freescale.com)
+ * Unified variable names for mpc83xx
*/
#include <common.h>
#include <asm/i2c.h>
#if defined(CONFIG_MPC8349EMDS) || defined(CONFIG_TQM834X)
-i2c_t * mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET);
+i2c_t * mpc83xx_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET);
#endif
void
writeb(0x00 , &I2C->cr);
/* set clock */
- writeb(0x3f, &I2C->fdr);
+ writeb(speed, &I2C->fdr);
/* set default filter */
writeb(0x10,&I2C->dfsrr);
/*
+ * (C) Copyright 2006 Freescale Semiconductor, Inc.
+ *
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
*
* 20050101: Eran Liberty (liberty@freescale.com)
* Initial file creating (porting from 85XX & 8260)
+ * 20060601: Dave Liu (daveliu@freescale.com)
+ * DDR ECC support
+ * unify variable names for 83xx
+ * code cleanup
*/
#include <common.h>
#ifdef CONFIG_SPD_EEPROM
-#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
extern void dma_init(void);
extern uint dma_check(void);
extern int dma_xfer(void *dest, uint count, void *src);
/*
* Convert picoseconds into clock cycles (rounding up if needed).
*/
+extern ulong get_ddr_clk(ulong dummy);
int
picos_to_clk(int picos)
{
+ unsigned int ddr_bus_clk;
int clks;
- clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
- if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
- clks++;
+ ddr_bus_clk = get_ddr_clk(0) >> 1;
+ clks = picos / ((1000000000 / ddr_bus_clk) * 1000);
+ if (picos % ((1000000000 / ddr_bus_clk) * 1000) !=0) {
+ clks++;
}
return clks;
long int spd_sdram()
{
volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
- volatile ddr8349_t *ddr = &immap->ddr;
- volatile law8349_t *ecm = &immap->sysconf.ddrlaw[0];
+ volatile ddr83xx_t *ddr = &immap->ddr;
+ volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
spd_eeprom_t spd;
- unsigned tmp, tmp1;
+ unsigned tmp;
unsigned int memsize;
unsigned int law_size;
- unsigned char caslat;
- unsigned int trfc, trfc_clk, trfc_low;
+ unsigned char caslat, caslat_ctrl;
+ unsigned char burstlen;
+ unsigned int max_bus_clk;
+ unsigned int max_data_rate, effective_data_rate;
+ unsigned int ddrc_clk;
+ unsigned int refresh_clk;
+ unsigned sdram_cfg;
+ unsigned int ddrc_ecc_enable;
+
+ /* Read SPD parameters with I2C */
CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
#ifdef SPD_DEBUG
spd_debug(&spd);
#endif
+ /* Check the memory type */
+ if (spd.mem_type != SPD_MEMTYPE_DDR) {
+ printf("DDR: Module mem type is %02X\n", spd.mem_type);
+ return 0;
+ }
+
+ /* Check the number of physical bank */
if (spd.nrows > 2) {
- puts("DDR:Only two chip selects are supported on ADS.\n");
+ printf("DDR: The number of physical bank is %02X\n", spd.nrows);
return 0;
}
- if (spd.nrow_addr < 12
- || spd.nrow_addr > 14
- || spd.ncol_addr < 8
- || spd.ncol_addr > 11) {
- puts("DDR:Row or Col number unsupported.\n");
+ /* Check if the number of row of the module is in the range of DDRC */
+ if (spd.nrow_addr < 12 || spd.nrow_addr > 14) {
+ printf("DDR: Row number is out of range of DDRC, row=%02X\n",
+ spd.nrow_addr);
return 0;
}
+ /* Check if the number of col of the module is in the range of DDRC */
+ if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
+ printf("DDR: Col number is out of range of DDRC, col=%02X\n",
+ spd.ncol_addr);
+ return 0;
+ }
+ /* Setup DDR chip select register */
ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
ddr->cs_config[2] = ( 1 << 31
| (spd.nrow_addr - 12) << 8
debug("DDR:ar=0x%08x\n", ecm->ar);
/*
- * find the largest CAS
+ * Find the largest CAS by locating the highest 1 bit
+ * in the spd.cas_lat field. Translate it to a DDR
+ * controller field value:
+ *
+ * CAS Lat DDR I Ctrl
+ * Clocks SPD Bit Value
+ * -------+--------+---------
+ * 1.0 0 001
+ * 1.5 1 010
+ * 2.0 2 011
+ * 2.5 3 100
+ * 3.0 4 101
+ * 3.5 5 110
+ * 4.0 6 111
*/
- if(spd.cas_lat & 0x40) {
- caslat = 7;
- } else if (spd.cas_lat & 0x20) {
- caslat = 6;
- } else if (spd.cas_lat & 0x10) {
- caslat = 5;
- } else if (spd.cas_lat & 0x08) {
- caslat = 4;
- } else if (spd.cas_lat & 0x04) {
- caslat = 3;
- } else if (spd.cas_lat & 0x02) {
- caslat = 2;
- } else if (spd.cas_lat & 0x01) {
- caslat = 1;
- } else {
- puts("DDR:no valid CAS Latency information.\n");
+ caslat = __ilog2(spd.cas_lat);
+
+ if (caslat > 4 ) {
+ printf("DDR: Invalid SPD CAS Latency, caslat=%02X\n", caslat);
return 0;
}
+ max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
+ + (spd.clk_cycle & 0x0f));
+ max_data_rate = max_bus_clk * 2;
+
+ debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate);
+
+ ddrc_clk = get_ddr_clk(0) / 1000000;
- tmp = 20000 / (((spd.clk_cycle & 0xF0) >> 4) * 10
- + (spd.clk_cycle & 0x0f));
- debug("DDR:Module maximum data rate is: %dMhz\n", tmp);
-
- tmp1 = get_bus_freq(0) / 1000000;
- if (tmp1 < 230 && tmp1 >= 90 && tmp >= 230) {
- /* 90~230 range, treated as DDR 200 */
- if (spd.clk_cycle3 == 0xa0)
- caslat -= 2;
- else if(spd.clk_cycle2 == 0xa0)
- caslat--;
- } else if (tmp1 < 280 && tmp1 >= 230 && tmp >= 280) {
- /* 230-280 range, treated as DDR 266 */
- if (spd.clk_cycle3 == 0x75)
- caslat -= 2;
- else if (spd.clk_cycle2 == 0x75)
- caslat--;
- } else if (tmp1 < 350 && tmp1 >= 280 && tmp >= 350) {
- /* 280~350 range, treated as DDR 333 */
- if (spd.clk_cycle3 == 0x60)
- caslat -= 2;
- else if (spd.clk_cycle2 == 0x60)
- caslat--;
- } else if (tmp1 < 90 || tmp1 >= 350) {
- /* DDR rate out-of-range */
- puts("DDR:platform frequency is not fit for DDR rate\n");
+ if (max_data_rate >= 390) { /* it is DDR 400 */
+ printf("DDR: platform not support DDR 400\n");
return 0;
+ } else if (max_data_rate >= 323) { /* it is DDR 333 */
+ if (ddrc_clk <= 350 && ddrc_clk > 280) {
+ /* DDRC clk at 280~350 */
+ effective_data_rate = 333; /* 6ns */
+ caslat = caslat;
+ } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
+ /* DDRC clk at 230~280 */
+ if (spd.clk_cycle2 == 0x75) {
+ effective_data_rate = 266; /* 7.5ns */
+ caslat = caslat - 1;
+ }
+ } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
+ /* DDRC clk at 90~230 */
+ if (spd.clk_cycle3 == 0xa0) {
+ effective_data_rate = 200; /* 10ns */
+ caslat = caslat - 2;
+ }
+ }
+ } else if (max_data_rate >= 256) { /* it is DDR 266 */
+ if (ddrc_clk <= 350 && ddrc_clk > 280) {
+ /* DDRC clk at 280~350 */
+ printf("DDR: DDR controller freq is more than "
+ "max data rate of the module\n");
+ return 0;
+ } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
+ /* DDRC clk at 230~280 */
+ effective_data_rate = 266; /* 7.5ns */
+ caslat = caslat;
+ } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
+ /* DDRC clk at 90~230 */
+ if (spd.clk_cycle2 == 0xa0) {
+ effective_data_rate = 200; /* 10ns */
+ caslat = caslat - 1;
+ }
+ }
+ } else if (max_data_rate >= 190) { /* it is DDR 200 */
+ if (ddrc_clk <= 350 && ddrc_clk > 230) {
+ /* DDRC clk at 230~350 */
+ printf("DDR: DDR controller freq is more than "
+ "max data rate of the module\n");
+ return 0;
+ } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
+ /* DDRC clk at 90~230 */
+ effective_data_rate = 200; /* 10ns */
+ caslat = caslat;
+ }
}
/*
* note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,
* use conservative value here.
*/
- trfc = spd.trfc * 1000; /* up to ps */
- trfc_clk = picos_to_clk(trfc);
- trfc_low = (trfc_clk - 8) & 0xf;
+ caslat_ctrl = (caslat + 1) & 0x07; /* see as above */
ddr->timing_cfg_1 =
(((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |
((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) |
((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) |
- ((caslat & 0x07) << 16 ) |
- (trfc_low << 12 ) |
+ ((caslat_ctrl & 0x07) << 16 ) |
+ (((picos_to_clk(spd.trfc * 1000) - 8) & 0x0f) << 12 ) |
( 0x300 ) |
((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1);
debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
+ /* Setup init value, but not enable */
+ ddr->sdram_cfg = 0x42000000;
+
+ /* Check DIMM data bus width */
+ if (spd.dataw_lsb == 0x20)
+ {
+ burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
+ printf("\n DDR DIMM: data bus width is 32 bit");
+ }
+ else
+ {
+ burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
+ printf("\n DDR DIMM: data bus width is 64 bit");
+ }
- /*
- * Only DDR I is supported
- * DDR I and II have different mode-register-set definition
+ /* Is this an ECC DDR chip? */
+ if (spd.config == 0x02) {
+ printf(" with ECC\n");
+ }
+ else
+ printf(" without ECC\n");
+
+ /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
+ Burst type is sequential
*/
switch(caslat) {
+ case 1:
+ ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
+ break;
case 2:
- tmp = 0x50; /* 1.5 */
+ ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
break;
case 3:
- tmp = 0x20; /* 2.0 */
+ ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
break;
case 4:
- tmp = 0x60; /* 2.5 */
- break;
- case 5:
- tmp = 0x30; /* 3.0 */
+ ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
break;
default:
- puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n");
+ printf("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 "
+ "is supported.\n");
return 0;
}
-#if defined (CONFIG_DDR_32BIT)
- /* set burst length to 8 for 32-bit data path */
- tmp |= 0x03;
-#else
- /* set burst length to 4 - default for 64-bit data path */
- tmp |= 0x02;
-#endif
- ddr->sdram_mode = tmp;
debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
switch(spd.refresh) {
ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
- /*
- * Is this an ECC DDR chip?
- */
-#if defined(CONFIG_DDR_ECC)
- if (spd.config == 0x02) {
- /* disable error detection */
- ddr->err_disable = ~ECC_ERROR_ENABLE;
+ /* SS_EN = 0, source synchronous disable
+ * CLK_ADJST = 0, MCK/MCK# is launched aligned with addr/cmd
+ */
+ ddr->sdram_clk_cntl = 0x00000000;
+ debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
- /* set single bit error threshold to maximum value,
- * reset counter to zero */
- ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
- (0 << ECC_ERROR_MAN_SBEC_SHIFT);
- }
- debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
- debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
-#endif
asm("sync;isync");
- udelay(500);
-
- /*
- * SS_EN=1,
- * CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM
- * clock cycle after address/command
- */
- /*ddr->sdram_clk_cntl = 0x82000000;*/
- ddr->sdram_clk_cntl = (DDR_SDRAM_CLK_CNTL_SS_EN|DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05);
+ udelay(600);
/*
* Figure out the settings for the sdram_cfg register. Build up
* sdram_cfg[0] = 1 (ddr sdram logic enable)
* sdram_cfg[1] = 1 (self-refresh-enable)
* sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM)
+ * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
+ * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
*/
- tmp = 0xc2000000;
+ sdram_cfg = 0xC2000000;
-#if defined (CONFIG_DDR_32BIT)
- /* in 32-Bit mode burst len is 8 beats */
- tmp |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
-#endif
- /*
- * sdram_cfg[3] = RD_EN - registered DIMM enable
- * A value of 0x26 indicates micron registered DIMMS (micron.com)
- */
- if (spd.mod_attr == 0x26) {
- tmp |= 0x10000000;
+ /* sdram_cfg[3] = RD_EN - registered DIMM enable */
+ if (spd.mod_attr & 0x02) {
+ sdram_cfg |= 0x10000000;
}
+ /* The DIMM is 32bit width */
+ if (spd.dataw_lsb == 0x20) {
+ sdram_cfg |= 0x000C0000;
+ }
+ ddrc_ecc_enable = 0;
+
#if defined(CONFIG_DDR_ECC)
- /*
- * If the user wanted ECC (enabled via sdram_cfg[2])
- */
+ /* Enable ECC with sdram_cfg[2] */
if (spd.config == 0x02) {
- tmp |= SDRAM_CFG_ECC_EN;
+ sdram_cfg |= 0x20000000;
+ ddrc_ecc_enable = 1;
+ /* disable error detection */
+ ddr->err_disable = ~ECC_ERROR_ENABLE;
+ /* set single bit error threshold to maximum value,
+ * reset counter to zero */
+ ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
+ (0 << ECC_ERROR_MAN_SBEC_SHIFT);
}
+
+ debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
+ debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
#endif
+ printf(" DDRC ECC mode: %s", ddrc_ecc_enable ? "ON":"OFF");
#if defined(CONFIG_DDR_2T_TIMING)
/*
* Enable 2T timing by setting sdram_cfg[16].
*/
- tmp |= SDRAM_CFG_2T_EN;
+ sdram_cfg |= SDRAM_CFG_2T_EN;
#endif
-
- ddr->sdram_cfg = tmp;
+ /* Enable controller, and GO! */
+ ddr->sdram_cfg = sdram_cfg;
asm("sync;isync");
udelay(500);
#endif /* CONFIG_SPD_EEPROM */
-#if defined(CONFIG_DDR_ECC)
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
/*
* Use timebase counter, get_timer() is not availabe
* at this point of initialization yet.
{
uint *p;
volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
- volatile ddr8349_t *ddr = &immap->ddr;
+ volatile ddr83xx_t *ddr= &immap->ddr;
unsigned long t_start, t_end;
#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
uint i;
return 0;
}
+ulong get_ddr_clk(ulong dummy)
+{
+ return gd->ddr_clk;
+}
+
+
/********************************************
* get_bus_freq
* return system bus freq in Hz
/*
* MPC8349 have two i2c bus
*/
-extern i2c_t * mpc8349_i2c;
-#define I2C mpc8349_i2c
+extern i2c_t * mpc83xx_i2c;
+#define I2C mpc83xx_i2c
#else
#define I2C ((i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET))
#endif
/*
- * MPC8349 Internal Memory Map
- * Copyright (c) 2004 Freescale Semiconductor.
- * Eran Liberty (liberty@freescale.com)
+ * (C) Copyright 2004-2006 Freescale Semiconductor, Inc.
+ *
+ * MPC83xx Internal Memory Map
+ *
+ * History :
+ * 20060601: Daveliu (daveliu@freescale.com)
+ * TanyaJiang (tanya.jiang@freescale.com)
+ * Unified variable names for mpc83xx
+ * 2005 : Mandy Lavi (mandy.lavi@freescale.com)
+ * support for mpc8360e
+ * 2004 : Eran Liberty (liberty@freescale.com)
+ * Initialized for mpc8349
+ * based on:
+ * MPC8260 Internal Memory Map
+ * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
+ * MPC85xx Internal Memory Map
+ * Copyright(c) 2002,2003 Motorola Inc.
+ * Xianghua Xiao (x.xiao@motorola.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
*
- * based on:
- * - MPC8260 Internal Memory Map
- * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
- * - MPC85xx Internal Memory Map
- * Copyright(c) 2002,2003 Motorola Inc.
- * Xianghua Xiao (x.xiao@motorola.com)
*/
-#ifndef __IMMAP_8349__
-#define __IMMAP_8349__
+#ifndef __IMMAP_83xx__
+#define __IMMAP_83xx__
+#include <config.h>
#include <asm/types.h>
#include <asm/i2c.h>
/*
* Local Access Window.
*/
-typedef struct law8349 {
+typedef struct law83xx {
u32 bar; /* LBIU local access window base address register */
/* Identifies the 20 most-significant address bits of the base of local
* access window n. The specified base address should be aligned to the
#define LAWBAR_BAR 0xFFFFF000
#define LAWBAR_RES ~(LAWBAR_BAR)
u32 ar; /* LBIU local access window attribute register */
-} law8349_t;
+} law83xx_t;
/*
* System configuration registers.
*/
-typedef struct sysconf8349 {
+typedef struct sysconf83xx {
u32 immrbar; /* Internal memory map base address register */
u8 res0[0x04];
u32 altcbar; /* Alternate configuration base address register */
#define ALTCBAR_BASE_ADDR 0xFFF00000
#define ALTCBAR_RES ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */
u8 res1[0x14];
- law8349_t lblaw[4]; /* LBIU local access window */
+ law83xx_t lblaw[4]; /* LBIU local access window */
u8 res2[0x20];
- law8349_t pcilaw[2]; /* PCI local access window */
+ law83xx_t pcilaw[2]; /* PCI local access window */
u8 res3[0x30];
- law8349_t ddrlaw[2]; /* DDR local access window */
+ law83xx_t ddrlaw[2]; /* DDR local access window */
u8 res4[0x50];
u32 sgprl; /* System General Purpose Register Low */
u32 sgprh; /* System General Purpose Register High */
#define SICRH_GPIO2_H 0x00000060
#define SICRH_TSOBI1 0x00000002
#define SICRH_TSOBI2 0x00000001
-#define SICRh_RES ~( SICRH_DDR | SICRH_TSEC1_A | SICRH_TSEC1_B \
+#define SICRH_RES ~( SICRH_DDR | SICRH_TSEC1_A | SICRH_TSEC1_B \
| SICRH_TSEC1_C | SICRH_TSEC1_D | SICRH_TSEC1_E \
| SICRH_TSEC1_F | SICRH_TSEC2_A | SICRH_TSEC2_B \
| SICRH_TSEC2_C | SICRH_TSEC2_D | SICRH_TSEC2_E \
| SICRH_GPIO2_G | SICRH_GPIO2_H | SICRH_TSOBI1 \
| SICRH_TSOBI2)
u8 res6[0xE4];
-} sysconf8349_t;
+} sysconf83xx_t;
/*
* Watch Dog Timer (WDT) Registers
*/
-typedef struct wdt8349 {
+typedef struct wdt83xx {
u8 res0[4];
u32 swcrr; /* System watchdog control register */
u32 swcnr; /* System watchdog count register */
#define SWCNR_RES ~(SWCNR_SWCN)
u8 res1[2];
u16 swsrr; /* System watchdog service register */
+#define SWSRR_WS 0x0000FFFF /* Software Watchdog Service Field.*/
u8 res2[0xF0];
-} wdt8349_t;
+} wdt83xx_t;
/*
* RTC/PIT Module Registers
*/
-typedef struct rtclk8349 {
+typedef struct rtclk83xx {
u32 cnr; /* control register */
#define CNR_CLEN 0x00000080 /* Clock Enable Control Bit */
#define CNR_CLIN 0x00000040 /* Input Clock Control Bit */
#define CNR_SIM 0x00000001 /* Second Interrupt Mask Bit */
#define CNR_RES ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM)
u32 ldr; /* load register */
+#define LDR_CLDV 0xFFFFFFFF /* Contains the 32-bit value to be
+ * loaded in a 32-bit RTC counter.*/
u32 psr; /* prescale register */
- u32 ctr; /* register */
+#define PSR_PRSC 0xFFFFFFFF /* RTC Prescaler bits.*/
+ u32 ctr; /* Counter value field register */
+#define CRT_CNTV 0xFFFFFFFF /* RTC Counter value field.*/
u32 evr; /* event register */
#define RTEVR_SIF 0x00000001 /* Second Interrupt Flag Bit */
#define RTEVR_AIF 0x00000002 /* Alarm Interrupt Flag Bit */
-#define RTEVR_RES ~(EVR_SIF | EVR_AIF)
+#define RTEVR_RES ~(RTEVR_SIF | RTEVR_AIF)
+#define PTEVR_PIF 0x00000001 /* Periodic interrupt flag bit.*/
+#define PTEVR_RES ~(PTEVR_PIF)
u32 alr; /* alarm register */
u8 res0[0xE8];
-} rtclk8349_t;
+} rtclk83xx_t;
/*
* Global timper module
*/
-typedef struct gtm8349 {
+typedef struct gtm83xx {
u8 cfr1; /* Timer1/2 Configuration */
#define CFR1_PCAS 0x80 /* Pair Cascade mode */
#define CFR1_BCM 0x40 /* Backward compatible mode */
#define CFR1_GM1 0x04 /* Gate mode for pin 1 */
#define CFR1_STP1 0x02 /* Stop timer */
#define CFR1_RST1 0x01 /* Reset timer */
+#define CFR1_RES ~(CFR1_PCAS | CFR1_STP2 | CFR1_RST2 | CFR1_GM2 |\
+ CFR1_GM1 | CFR1_STP1 | CFR1_RST1)
u8 res0[3];
u8 cfr2; /* Timer3/4 Configuration */
#define CFR2_PCAS 0x80 /* Pair Cascade mode */
u16 psr2; /* Timer2 Prescaler Register */
u16 psr3; /* Timer3 Prescaler Register */
u16 psr4; /* Timer4 Prescaler Register */
+#define GTPSR_PPS 0x00FF /* Primary Prescaler Bits. */
+#define GTPSR_RES ~(GTPSR_PPS)
u8 res[0xC0];
-} gtm8349_t;
+} gtm83xx_t;
/*
* Integrated Programmable Interrupt Controller
*/
-typedef struct ipic8349 {
+typedef struct ipic83xx {
u32 sicfr; /* System Global Interrupt Configuration Register (SICFR) */
#define SICFR_HPI 0x7f000000 /* Highest Priority Interrupt */
#define SICFR_MPSB 0x00400000 /* Mixed interrupts Priority Scheme for group B */
#define SIIH_UART2 0x00000040 /* UART2 interrupt */
#define SIIH_SEC 0x00000020 /* SEC interrupt */
#define SIIH_I2C1 0x00000004 /* I2C1 interrupt */
-#define SIIH_I2C2 0x00000002 /* I2C1 interrupt */
+#define SIIH_I2C2 0x00000002 /* I2C2 interrupt */
#define SIIH_SPI 0x00000001 /* SPI interrupt */
#define SIIH_RES ~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \
| SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \
u32 sifcr_l; /* System Internal Interrupt Force Register - Low (SIIL) */
u32 sefcr; /* System External Interrupt Force Register (SEI) */
u32 serfr; /* System Error Force Register (SERR) */
- u8 res3[0xA0];
-} ipic8349_t;
+ u32 scvcr; /* System Critical Interrupt Vector Register */
+#define SCVCR_CVECX 0xFC000000 /* Backward (MPC8260) compatible
+ critical interrupt vector. */
+#define SCVCR_CVEC 0x0000007F /* Critical interrupt vector */
+#define SCVCR_RES ~(SCVCR_CVECX|SCVCR_CVEC)
+ u32 smvcr; /* System Management Interrupt Vector Register */
+#define SMVCR_CVECX 0xFC000000 /* Backward (MPC8260) compatible
+ critical interrupt vector. */
+#define SMVCR_CVEC 0x0000007F /* Critical interrupt vector */
+#define SMVCR_RES ~(SMVCR_CVECX|SMVCR_CVEC)
+ u8 res3[0x98];
+} ipic83xx_t;
/*
* System Arbiter Registers
*/
-typedef struct arbiter8349 {
+typedef struct arbiter83xx {
u32 acr; /* Arbiter Configuration Register */
#define ACR_COREDIS 0x10000000 /* Core disable. */
#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth (number of outstanding transactions). */
#define AE_ATO 0x00000001 /* Address time out. */
#define AE_RSRV ~(AE_ETEA|AE_RES_|AE_ECW|AE_AO|AE_DTO|AE_ATO)
u8 res1[0xDC];
-} arbiter8349_t;
+} arbiter83xx_t;
/*
* Reset Module
*/
-typedef struct reset8349 {
+typedef struct reset83xx {
u32 rcwl; /* RCWL Register */
#define RCWL_LBIUCM 0x80000000 /* LBIUCM */
#define RCWL_LBIUCM_SHIFT 31
#define RCWL_CEVCOD 0x000000C0 /* CEVCOD */
#define RCWL_CEPDF 0x00000020 /* CEPDF */
#define RCWL_CEPMF 0x0000001F /* CEPMF */
-#define RCWL_RES ~(RCWL_BIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF)
+#define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF)
u32 rcwh; /* RCHL Register */
#define RCWH_PCIHOST 0x80000000 /* PCIHOST */
#define RCWH_PCIHOST_SHIFT 31
#define RCER_CRE 0x00000001 /* software hard reset */
#define RCER_RES ~(RCER_CRE)
u8 res1[0xDC];
-} reset8349_t;
+} reset83xx_t;
-typedef struct clk8349 {
+typedef struct clk83xx {
u32 spmr; /* system PLL mode Register */
#define SPMR_LBIUCM 0x80000000 /* LBIUCM */
#define SPMR_DDRCM 0x40000000 /* DDRCM */
#define SCCR_RES ~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \
| SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM)
u8 res0[0xF4];
-} clk8349_t;
+} clk83xx_t;
/*
* Power Management Control Module
*/
-typedef struct pmc8349 {
+typedef struct pmc83xx {
u32 pmccr; /* PMC Configuration Register */
#define PMCCR_SLPEN 0x00000001 /* System Low Power Enable */
#define PMCCR_DLPEN 0x00000002 /* DDR SDRAM Low Power Enable */
-#define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN)
+#define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN)
u32 pmcer; /* PMC Event Register */
#define PMCER_PMCI 0x00000001 /* PMC Interrupt */
#define PMCER_RES ~(PMCER_PMCI)
#define PMCMR_PMCIE 0x0001 /* PMC Interrupt Enable */
#define PMCMR_RES ~(PMCMR_PMCIE)
u8 res0[0xF4];
-} pmc8349_t;
-
+} pmc83xx_t;
/*
* general purpose I/O module
*/
-typedef struct gpio8349 {
+typedef struct gpio83xx {
u32 dir; /* direction register */
u32 odr; /* open drain register */
u32 dat; /* data register */
u32 imr; /* interrupt mask register */
u32 icr; /* external interrupt control register */
u8 res0[0xE8];
-} gpio8349_t;
+} gpio83xx_t;
/*
* DDR Memory Controller Memory Map
u8 res0[4];
} ddr_cs_bnds_t;
-typedef struct ddr8349{
+typedef struct ddr83xx {
ddr_cs_bnds_t csbnds[4]; /**< Chip Select x Memory Bounds */
u8 res0[0x60];
u32 cs_config[4]; /**< Chip Select x Configuration */
u8 res7[0xA4];
u32 debug_reg;
u8 res8[0xFC];
-} ddr8349_t;
+} ddr83xx_t;
/*
* I2C1 Controller
/*
* DUART
*/
-typedef struct duart8349{
+typedef struct duart83xx{
u8 urbr_ulcr_udlb; /**< combined register for URBR, UTHR and UDLB */
u8 uier_udmb; /**< combined register for UIER and UDMB */
u8 uiir_ufcr_uafr; /**< combined register for UIIR, UFCR and UAFR */
u8 udsr; /**< DMA status register */
u8 res1[3];
u8 res2[0xEC];
-} duart8349_t;
+} duart83xx_t;
/*
* Local Bus Controller Registers
u32 or; /**< Base Register */
} lbus_bank_t;
-typedef struct lbus8349 {
+typedef struct lbus83xx {
lbus_bank_t bank[8];
u8 res0[0x28];
u32 mar; /**< UPM Address Register */
u8 res7[0x28];
u8 res8[0xF00];
-} lbus8349_t;
+} lbus83xx_t;
/*
* Serial Peripheral Interface
*/
-typedef struct spi8349
+typedef struct spi83xx
{
u32 mode; /**< mode register */
u32 event; /**< event register */
u32 tx; /**< transmit register */
u32 rx; /**< receive register */
u8 res1[0xD8];
-} spi8349_t;
+} spi83xx_t;
/*
* DMA/Messaging Unit
*/
-typedef struct dma8349 {
+typedef struct dma83xx {
u32 res0[0xC]; /* 0x0-0x29 reseverd */
u32 omisr; /* 0x30 Outbound message interrupt status register */
u32 omimr; /* 0x34 Outbound message interrupt mask register */
u32 dmagsr; /* 0x2A8 DMA general status register */
u32 res20[0x15];/* 0x2AC-0x2FF reserved */
-} dma8349_t;
+} dma83xx_t;
/* DMAMRn bits */
#define DMA_CHANNEL_START (0x00000001) /* Bit - DMAMRn CS */
/*
* PCI Software Configuration Registers
*/
-typedef struct pciconf8349 {
+typedef struct pciconf83xx {
u32 config_address;
#define PCI_CONFIG_ADDRESS_EN 0x80000000
#define PCI_CONFIG_ADDRESS_BN_SHIFT 16
u32 config_data;
u32 int_ack;
u8 res[116];
-} pciconf8349_t;
+} pciconf83xx_t;
/*
* PCI Outbound Translation Register
u8 res1[4];
u32 pocmr;
u8 res2[4];
-} pot8349_t;
+} pot83xx_t;
/*
* Sequencer
*/
-typedef struct ios8349 {
- pot8349_t pot[6];
+typedef struct ios83xx {
+ pot83xx_t pot[6];
#define POTAR_TA_MASK 0x000fffff
#define POBAR_BA_MASK 0x000fffff
#define POCMR_EN 0x80000000
u8 res1[4];
u32 dtcr;
u8 res2[4];
-} ios8349_t;
+} ios83xx_t;
/*
* PCI Controller Control and Status Registers
*/
-typedef struct pcictrl8349 {
+typedef struct pcictrl83xx {
u32 esr;
#define ESR_MERR 0x80000000
#define ESR_APAR 0x00000400
#define PIWAR_IWS_512M 0x0000001C
#define PIWAR_IWS_1G 0x0000001D
#define PIWAR_IWS_2G 0x0000001E
-} pcictrl8349_t;
+} pcictrl83xx_t;
/*
* USB
*/
-typedef struct usb8349 {
+typedef struct usb83xx {
u8 fixme[0x2000];
-} usb8349_t;
+} usb83xx_t;
/*
* TSEC
*/
-typedef struct tsec8349 {
+typedef struct tsec83xx {
u8 fixme[0x1000];
-} tsec8349_t;
+} tsec83xx_t;
/*
* Security
*/
-typedef struct security8349 {
+typedef struct security83xx {
u8 fixme[0x10000];
-} security8349_t;
+} security83xx_t;
typedef struct immap {
- sysconf8349_t sysconf; /* System configuration */
- wdt8349_t wdt; /* Watch Dog Timer (WDT) Registers */
- rtclk8349_t rtc; /* Real Time Clock Module Registers */
- rtclk8349_t pit; /* Periodic Interval Timer */
- gtm8349_t gtm[2]; /* Global Timers Module */
- ipic8349_t ipic; /* Integrated Programmable Interrupt Controller */
- arbiter8349_t arbiter; /* System Arbiter Registers */
- reset8349_t reset; /* Reset Module */
- clk8349_t clk; /* System Clock Module */
- pmc8349_t pmc; /* Power Management Control Module */
- gpio8349_t pgio[2]; /* general purpose I/O module */
+ sysconf83xx_t sysconf; /* System configuration */
+ wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
+ rtclk83xx_t rtc; /* Real Time Clock Module Registers */
+ rtclk83xx_t pit; /* Periodic Interval Timer */
+ gtm83xx_t gtm[2]; /* Global Timers Module */
+ ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
+ arbiter83xx_t arbiter; /* System Arbiter Registers */
+ reset83xx_t reset; /* Reset Module */
+ clk83xx_t clk; /* System Clock Module */
+ pmc83xx_t pmc; /* Power Management Control Module */
+ gpio83xx_t pgio[2]; /* general purpose I/O module */
u8 res0[0x200];
u8 DDL_DDR[0x100];
u8 DDL_LBIU[0x100];
u8 res1[0xE00];
- ddr8349_t ddr; /* DDR Memory Controller Memory */
+ ddr83xx_t ddr; /* DDR Memory Controller Memory */
i2c_t i2c[2]; /* I2C1 Controller */
u8 res2[0x1300];
- duart8349_t duart[2];/* DUART */
+ duart83xx_t duart[2];/* DUART */
u8 res3[0x900];
- lbus8349_t lbus; /* Local Bus Controller Registers */
+ lbus83xx_t lbus; /* Local Bus Controller Registers */
u8 res4[0x1000];
- spi8349_t spi; /* Serial Peripheral Interface */
+ spi83xx_t spi; /* Serial Peripheral Interface */
u8 res5[0xF00];
- dma8349_t dma; /* DMA */
- pciconf8349_t pci_conf[2]; /* PCI Software Configuration Registers */
- ios8349_t ios; /* Sequencer */
- pcictrl8349_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */
+ dma83xx_t dma; /* DMA */
+ pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */
+ ios83xx_t ios; /* Sequencer */
+ pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */
u8 res6[0x19900];
- usb8349_t usb;
- tsec8349_t tsec[2];
+ usb83xx_t usb;
+ tsec83xx_t tsec[2];
u8 res7[0xA000];
- security8349_t security;
+ security83xx_t security;
} immap_t;
-#endif /* __IMMAP_8349__ */
+#endif /* __IMMAP_83xx__ */
/*
- * Copyright 2004 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
#ifndef __MPC83XX_H__
#define __MPC83XX_H__
+#include <config.h>
#if defined(CONFIG_E300)
#include <asm/e300.h>
#endif
#define LBLAWBAR3 0x0038
#define LBLAWAR3 0x003C
+/*
+ * The device ID and revision numbers
+ */
+#define SPR_8349E_REV10 0x80300100
+#define SPR_8349E_REV11 0x80300101
/*
* Base Registers & Option Registers
#define HRCWH_BIG_ENDIAN 0x00000000
#define HRCWH_LITTLE_ENDIAN 0x00000008
+#define HRCWH_LALE_NORMAL 0x00000000
+#define HRCWH_LALE_EARLY 0x00000004
+
+#define HRCWH_LDP_SET 0x00000000
+#define HRCWH_LDP_CLEAR 0x00000002
+
/*
* Hard Reset Configration Word - Low
*/
#define LCRR_CLKDIV_8 0x00000008
#define LCRR_CLKDIV_SHIFT 0
+/*
+ * SCCR-System Clock Control Register
+ */
+#define SCCR_TSEC1CM_0 0x00000000
+#define SCCR_TSEC1CM_1 0x40000000
+#define SCCR_TSEC1CM_2 0x80000000
+#define SCCR_TSEC1CM_3 0xC0000000
+#define SCCR_TSEC2CM_0 0x00000000
+#define SCCR_TSEC2CM_1 0x10000000
+#define SCCR_TSEC2CM_2 0x20000000
+#define SCCR_TSEC2CM_3 0x30000000
+#define SCCR_ENCCM_0 0x00000000
+#define SCCR_ENCCM_1 0x01000000
+#define SCCR_ENCCM_2 0x02000000
+#define SCCR_ENCCM_3 0x03000000
+#define SCCR_USBCM_0 0x00000000
+#define SCCR_USBCM_1 0x00500000
+#define SCCR_USBCM_2 0x00A00000
+#define SCCR_USBCM_3 0x00F00000
+
+#define SCCR_CLK_MASK ( SCCR_TSEC1CM_3 \
+ | SCCR_TSEC2CM_3 \
+ | SCCR_ENCCM_3 \
+ | SCCR_USBCM_3 )
+#define SCCR_DEFAULT 0xFFFFFFFF
+
#endif /* __MPC83XX_H__ */
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