arm64: zynqmp: Assign TSU clock frequency for KR260

Set TSU clock frequency as 250MHz (minimum when running at 1G) on
KR260 CC to allow PTP functionality.

Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/d065b5c2c6450910bf57d104d65946111493caaa.1688992653.git.michal.simek@amd.com

diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index 4d44924f6633089711b3435c1ed4348bbea8e627..a21dca87d248726d65958024c9238a1c5f7be12f 100644 (file)
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -169,24 +169,28 @@
        clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
                 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
                 <&zynqmp_clk GEM_TSU>;
+       assigned-clocks = <&zynqmp_clk GEM_TSU>;
 };
 
 &gem1 {
        clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
                 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
                 <&zynqmp_clk GEM_TSU>;
+       assigned-clocks = <&zynqmp_clk GEM_TSU>;
 };
 
 &gem2 {
        clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
                 <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
                 <&zynqmp_clk GEM_TSU>;
+       assigned-clocks = <&zynqmp_clk GEM_TSU>;
 };
 
 &gem3 {
        clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
                 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
                 <&zynqmp_clk GEM_TSU>;
+       assigned-clocks = <&zynqmp_clk GEM_TSU>;
 };
 
 &gpio {

diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
index 5ac66bc1ec5fe8ae525e48190acfc5861a95fd02..caaf71d729e4c918f2bfb76288261229e4bd68dc 100644 (file)
--- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts
@@ -188,6 +188,7 @@
        phy-handle = <&phy0>;
        phy-mode = "sgmii";
        is-internal-pcspma;
+       assigned-clock-rates = <250000000>;
 };
 
 &gem1 { /* mdio mio50/51, gem mio38 - mio49 */
@@ -196,6 +197,7 @@
        pinctrl-0 = <&pinctrl_gem1_default>;
        phy-handle = <&phy1>;
        phy-mode = "rgmii-id";
+       assigned-clock-rates = <250000000>;
 
        mdio: mdio {
                #address-cells = <1>;

diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
index 401de9efb913f29c55b690f7126205b373a7c6a6..f9d87559a719af12c1f8dcb7ef30e5ff630449b9 100644 (file)
--- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
+++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts
@@ -188,6 +188,7 @@
        phy-handle = <&phy0>;
        phy-mode = "sgmii";
        is-internal-pcspma;
+       assigned-clock-rates = <250000000>;
 };
 
 &gem1 { /* mdio mio50/51, gem mio38 - mio49 */
@@ -196,6 +197,7 @@
        pinctrl-0 = <&pinctrl_gem1_default>;
        phy-handle = <&phy1>;
        phy-mode = "rgmii-id";
+       assigned-clock-rates = <250000000>;
 
        mdio: mdio {
                #address-cells = <1>;