ARM: zynq: slcr: Dont modify the reserved bits

Set only the 0-3 bits of the FPGA_RST_CTRL register
as other bits should not be set to 1.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Nathan Rossi <nathan.rossi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c
index 934ccc31c86fd80723afa6c89be03c5651600cb9..2521589c07e9cf0c07a2f59990a521aafcfea7c8 100644 (file)
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/cpu/armv7/zynq/slcr.c
@@ -132,7 +132,7 @@ void zynq_slcr_devcfg_disable(void)
        zynq_slcr_unlock();
 
        /* Disable AXI interface by asserting FPGA resets */
-       writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
+       writel(0xF, &slcr_base->fpga_rst_ctrl);
 
        /* Set Level Shifters DT618760 */
        writel(0xA, &slcr_base->lvl_shftr_en);