powerpc/85xx: Rework MPC8548CDS pci_init_board to use common FSL PCIe code

Remove duplicated code in MPC8548CDS board and utilize the common
fsl_pcie_init_board().  We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c
index 98748aa478c8ce85507a142cecb313529f7b4b9b..e59fee807dd1621fb78ff79d8bb3f607ac045582 100644 (file)
--- a/board/freescale/mpc8548cds/law.c
+++ b/board/freescale/mpc8548cds/law.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008,2010 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -51,17 +51,9 @@
  */
 
 struct law_entry law_table[] = {
-#ifdef CONFIG_SYS_PCI1_MEM_PHYS
-       SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-       SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
-#endif
 #ifdef CONFIG_SYS_PCI2_MEM_PHYS
        SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
        SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
-#endif
-#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
-       SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
-       SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
 #endif
        /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
        SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),

diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index 2c455853a81ae5aed3f6b038373f2f7298156740..f5c799b9f9d6ebd38736bb626ec75fe6e23d9016 100644 (file)
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -215,20 +215,13 @@ static struct pci_controller pci1_hose = {
 static struct pci_controller pci2_hose;
 #endif /* CONFIG_PCI2 */
 
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif /* CONFIG_PCIE1 */
-
 void pci_init_board(void)
 {
        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-       struct fsl_pci_info pci_info[4];
+       struct fsl_pci_info pci_info;
        u32 devdisr, pordevsr, io_sel;
        u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
        int first_free_busno = 0;
-       int num = 0;
-
-       int pcie_ep, pcie_configured;
 
        devdisr = in_be32(&gur->devdisr);
        pordevsr = in_be32(&gur->pordevsr);
@@ -244,8 +237,13 @@ void pci_init_board(void)
        pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
 
        if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
-               SET_STD_PCI_INFO(pci_info[num], 1);
-               pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
+               SET_STD_PCI_INFO(pci_info, 1);
+               set_next_law(pci_info.mem_phys,
+                       law_size_bits(pci_info.mem_size), pci_info.law);
+               set_next_law(pci_info.io_phys,
+                       law_size_bits(pci_info.io_size), pci_info.law);
+
+               pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
                printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
                        (pci_32) ? 32 : 64,
                        (pci_speed == 33333000) ? "33" :
@@ -253,9 +251,9 @@ void pci_init_board(void)
                        pci_clk_sel ? "sync" : "async",
                        pci_agent ? "agent" : "host",
                        pci_arb ? "arbiter" : "external-arbiter",
-                       pci_info[num].regs);
+                       pci_info.regs);
 
-               first_free_busno = fsl_pci_init_port(&pci_info[num++],
+               first_free_busno = fsl_pci_init_port(&pci_info,
                                        &pci1_hose, first_free_busno);
 
 #ifdef CONFIG_PCIX_CHECK
@@ -293,26 +291,7 @@ void pci_init_board(void)
        setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
 #endif /* CONFIG_PCI2 */
 
-#ifdef CONFIG_PCIE1
-       pcie_configured = is_serdes_configured(PCIE1);
-
-       if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
-               SET_STD_PCIE_INFO(pci_info[num], 1);
-               pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
-               printf("PCIE1: connected to Slot as %s (base addr %lx)\n",
-                       pcie_ep ? "Endpoint" : "Root Complex",
-                       pci_info[num].regs);
-
-               first_free_busno = fsl_pci_init_port(&pci_info[num++],
-                                       &pcie1_hose, first_free_busno);
-       } else {
-               printf("PCIE1: disabled\n");
-       }
-
-       puts("\n");
-#else
-       setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
-#endif
+       fsl_pcie_init_board(first_free_busno);
 }
 
 int last_stage_init(void)

diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index e5ac3a950410137d1b56568d8a6b8d788c8c172e..4c5b998423f8881da7286ac88c6c54403a4ff906 100644 (file)
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004, 2007 Freescale Semiconductor.
+ * Copyright 2004, 2007, 2010 Freescale Semiconductor.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -353,6 +353,7 @@ extern unsigned long get_clock_freq(void);
 #endif
 
 #ifdef CONFIG_PCIE1
+#define CONFIG_SYS_PCIE1_NAME          "Slot"
 #define CONFIG_SYS_PCIE1_MEM_VIRT      0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_BUS       0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS      0xa0000000