Patch by Steven Scholz, 13 March 2005:

fix cache enabling for AT91RM9200

diff --git a/CHANGELOG b/CHANGELOG
index d7dcec7ea8ab9d3d1b9fed5a867185e2445aedb3..9bdace71aadc84361dd7854ffd91b7c81186c10d 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
 Changes for U-Boot 1.1.3:
 ======================================================================
 
+* Patch by Steven Scholz, 13 March 2005:
+  fix cache enabling for AT91RM9200
+
 * Patch by Masami Komiya, 30 Mar 2005:
   add SNTP support and expand time server and time offset fields of
   DHCP support. See doc/README.SNTP

diff --git a/cpu/at91rm9200/start.S b/cpu/at91rm9200/start.S
index 43ab93db611869b3c48c867b7d8a46bf5904d61a..0dbc0094a4a2a17350272e35e515a94cf62a6486 100644 (file)
--- a/cpu/at91rm9200/start.S
+++ b/cpu/at91rm9200/start.S
@@ -127,21 +127,20 @@ reset:
         * is why it's called lowlevelinit
         */
        bl      lowlevelinit /* in lowlevel.S */
-       bl      icache_enable;
-       /*------------------------------------
-         Read/modify/write CP15 control register
-        -------------------------------------
-         read cp15 control register (cp15 r1) in r0
-         ------------------------------------*/
-       mrc     p15, 0, r0, c1, c0, 0
-       /* Reset bit :Little Endian end fast bus mode */
-       ldr     r3, =0xC0000080
-       /* Set bit :Asynchronous clock mode, Not Fast Bus */
-       ldr     r4, =0xC0000000
-       bic     r0, r0, r3
-       orr     r0, r0, r4
-       /* write r0 in cp15 control register (cp15 r1) */
-       mcr     p15, 0, r0, c1, c0, 0
+
+       /*
+        * Read/modify/write CP15 control register
+        * disable MMU, enable I-Cache, select Asychronous Clocking Mode
+        */
+
+       mrc     p15, 0, r0, c1, c0, 0   @ read cp15 control register (cp15 r1) in r0
+       bic     r0, r0, #0x00002300     @ clear bits 13, 9:8 (--V- --RS)
+       bic     r0, r0, #0x0000008f     @ clear bits 7, 3:0 (B--- WCAM)
+       orr     r0, r0, #0x00000002     @ set bit 2 (A) Align
+       orr     r0, r0, #0x00000004     @ set bit 3 (C) D-Cache
+       orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
+       orr     r0, r0, #0xC0000000     @ set bits 31:30 (iA, nF)
+       mcr     p15, 0, r0, c1, c0, 0   @ write r0 in cp15 control register (cp15 r1)
 #endif /* CONFIG_BOOTBINFUNC */
        /*
         * relocate exeception table