ARM: tegra: error check Tegra210 XUSB padctl waits

Add code to detect timeouts when waiting for HW events such as PLL
lock done. Any errors are logged and trigger an error return code.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
index 6022f1614bdaf29d563d2f8e71309d6305cbe0b4..9ec93e7c4c4c0ce4ad14f2feaaedb4c6e9f296c6 100644 (file)
--- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c
+++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
@@ -279,7 +279,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
                if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)
                        break;
        }
-
+       if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE)) {
+               debug("  timeout\n");
+               return -ETIMEDOUT;
+       }
        debug("  done\n");
 
        value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
@@ -295,7 +298,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
                if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) == 0)
                        break;
        }
-
+       if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_DONE) {
+               debug("  timeout\n");
+               return -ETIMEDOUT;
+       }
        debug("  done\n");
 
        value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
@@ -310,7 +316,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
                if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)
                        break;
        }
-
+       if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL1_LOCKDET_STATUS)) {
+               debug("  timeout\n");
+               return -ETIMEDOUT;
+       }
        debug("  done\n");
 
        value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
@@ -326,7 +335,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
                if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)
                        break;
        }
-
+       if (!(value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE)) {
+               debug("  timeout\n");
+               return -ETIMEDOUT;
+       }
        debug("  done\n");
 
        value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
@@ -341,7 +353,10 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
                if ((value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) == 0)
                        break;
        }
-
+       if (value & XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_DONE) {
+               debug("  timeout\n");
+               return -ETIMEDOUT;
+       }
        debug("  done\n");
 
        value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);