riscv: dts: jh7110: Add initial StarFive VisionFive v2 board device tree

Add initial device tree for StarFive VisionFive v2 board.

Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index c576c55767f52b1cc3c107564a0114bed1788622..79a58694f534942c78e514ae11502a46717cf31e 100644 (file)
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -7,7 +7,8 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
 dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
-
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.3b.dtb
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.2a.dtb
 include $(srctree)/scripts/Makefile.dts
 
 targets += $(dtb-y)

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
new file mode 100644 (file)
index 0000000..3c322c5
--- /dev/null
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a-u-boot.dtsi
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include "binman.dtsi"
+#include "jh7110-u-boot.dtsi"
+/ {
+       chosen {
+               bootph-pre-ram;
+       };
+
+       firmware {
+               spi0 = &qspi;
+               bootph-pre-ram;
+       };
+
+       config {
+               bootph-pre-ram;
+               u-boot,spl-payload-offset = <0x100000>;
+       };
+
+       memory@40000000 {
+               bootph-pre-ram;
+       };
+};
+
+&uart0 {
+       bootph-pre-ram;
+};
+
+&mmc0 {
+       bootph-pre-ram;
+};
+
+&mmc1 {
+       bootph-pre-ram;
+};
+
+&qspi {
+       bootph-pre-ram;
+
+       nor-flash@0 {
+               bootph-pre-ram;
+       };
+};
+
+&sysgpio {
+       bootph-pre-ram;
+};
+
+&mmc0_pins {
+       bootph-pre-ram;
+       mmc0-pins-rest {
+               bootph-pre-ram;
+       };
+};
+
+&mmc1_pins {
+       bootph-pre-ram;
+       mmc1-pins0 {
+               bootph-pre-ram;
+       };
+
+       mmc1-pins1 {
+               bootph-pre-ram;
+       };
+};
+

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
new file mode 100644 (file)
index 0000000..b9d26d7
--- /dev/null
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.2a.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+#include "jh7110-starfive-visionfive-2.dtsi"
+
+/ {
+       model = "StarFive VisionFive 2 v1.2A";
+       compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
+};

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
new file mode 100644 (file)
index 0000000..3c322c5
--- /dev/null
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include "binman.dtsi"
+#include "jh7110-u-boot.dtsi"
+/ {
+       chosen {
+               bootph-pre-ram;
+       };
+
+       firmware {
+               spi0 = &qspi;
+               bootph-pre-ram;
+       };
+
+       config {
+               bootph-pre-ram;
+               u-boot,spl-payload-offset = <0x100000>;
+       };
+
+       memory@40000000 {
+               bootph-pre-ram;
+       };
+};
+
+&uart0 {
+       bootph-pre-ram;
+};
+
+&mmc0 {
+       bootph-pre-ram;
+};
+
+&mmc1 {
+       bootph-pre-ram;
+};
+
+&qspi {
+       bootph-pre-ram;
+
+       nor-flash@0 {
+               bootph-pre-ram;
+       };
+};
+
+&sysgpio {
+       bootph-pre-ram;
+};
+
+&mmc0_pins {
+       bootph-pre-ram;
+       mmc0-pins-rest {
+               bootph-pre-ram;
+       };
+};
+
+&mmc1_pins {
+       bootph-pre-ram;
+       mmc1-pins0 {
+               bootph-pre-ram;
+       };
+
+       mmc1-pins1 {
+               bootph-pre-ram;
+       };
+};
+

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
new file mode 100644 (file)
index 0000000..3b3b345
--- /dev/null
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+#include "jh7110-starfive-visionfive-2.dtsi"
+
+/ {
+       model = "StarFive VisionFive 2 v1.3B";
+       compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
+};

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
new file mode 100644 (file)
index 0000000..c6b6dfa
--- /dev/null
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -0,0 +1,319 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include "jh7110.dtsi"
+#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
+/ {
+       aliases {
+               serial0 = &uart0;
+               spi0 = &qspi;
+               mmc0 = &mmc0;
+               mmc1 = &mmc1;
+               i2c0 = &i2c0;
+               i2c2 = &i2c2;
+               i2c5 = &i2c5;
+               i2c6 = &i2c6;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       cpus {
+               timebase-frequency = <4000000>;
+       };
+
+       memory@40000000 {
+               device_type = "memory";
+               reg = <0x0 0x40000000 0x2 0x0>;
+       };
+};
+
+&osc {
+       clock-frequency = <24000000>;
+};
+
+&rtc_osc {
+       clock-frequency = <32768>;
+};
+
+&gmac0_rmii_refin {
+       clock-frequency = <50000000>;
+};
+
+&gmac0_rgmii_rxin {
+       clock-frequency = <125000000>;
+};
+
+&gmac1_rmii_refin {
+       clock-frequency = <50000000>;
+};
+
+&gmac1_rgmii_rxin {
+       clock-frequency = <125000000>;
+};
+
+&i2stx_bclk_ext {
+       clock-frequency = <12288000>;
+};
+
+&i2stx_lrck_ext {
+       clock-frequency = <192000>;
+};
+
+&i2srx_bclk_ext {
+       clock-frequency = <12288000>;
+};
+
+&i2srx_lrck_ext {
+       clock-frequency = <192000>;
+};
+
+&tdm_ext {
+       clock-frequency = <49152000>;
+};
+
+&mclk_ext {
+       clock-frequency = <12288000>;
+};
+
+&uart0 {
+       reg-offset = <0>;
+       current-speed = <115200>;
+       clock-frequency = <24000000>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&uart0_pins>;
+       status = "okay";
+};
+
+&i2c0 {
+       clock-frequency = <100000>;
+       i2c-sda-hold-time-ns = <300>;
+       i2c-sda-falling-time-ns = <510>;
+       i2c-scl-falling-time-ns = <510>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c0_pins>;
+       status = "okay";
+};
+
+&i2c2 {
+       clock-frequency = <100000>;
+       i2c-sda-hold-time-ns = <300>;
+       i2c-sda-falling-time-ns = <510>;
+       i2c-scl-falling-time-ns = <510>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c2_pins>;
+       status = "okay";
+};
+
+&i2c5 {
+       clock-frequency = <100000>;
+       i2c-sda-hold-time-ns = <300>;
+       i2c-sda-falling-time-ns = <510>;
+       i2c-scl-falling-time-ns = <510>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c5_pins>;
+       status = "okay";
+};
+
+&i2c6 {
+       clock-frequency = <100000>;
+       i2c-sda-hold-time-ns = <300>;
+       i2c-sda-falling-time-ns = <510>;
+       i2c-scl-falling-time-ns = <510>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c6_pins>;
+       status = "okay";
+};
+
+&sysgpio {
+       status = "okay";
+       uart0_pins: uart0-0 {
+               tx-pins {
+                       pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
+                                            GPOEN_ENABLE,
+                                            GPI_NONE)>;
+                       bias-disable;
+                       drive-strength = <12>;
+                       input-disable;
+                       input-schmitt-disable;
+                       slew-rate = <0>;
+               };
+
+               rx-pins {
+                       pinmux = <GPIOMUX(6, GPOUT_LOW,
+                                            GPOEN_DISABLE,
+                                            GPI_SYS_UART0_RX)>;
+                       bias-disable; /* external pull-up */
+                       drive-strength = <2>;
+                       input-enable;
+                       input-schmitt-enable;
+                       slew-rate = <0>;
+               };
+       };
+
+       i2c0_pins: i2c0-0 {
+               i2c-pins {
+                       pinmux = <GPIOMUX(57, GPOUT_LOW,
+                                             GPOEN_SYS_I2C0_CLK,
+                                             GPI_SYS_I2C0_CLK)>,
+                                <GPIOMUX(58, GPOUT_LOW,
+                                             GPOEN_SYS_I2C0_DATA,
+                                             GPI_SYS_I2C0_DATA)>;
+                       bias-disable; /* external pull-up */
+                       input-enable;
+                       input-schmitt-enable;
+               };
+       };
+
+       i2c2_pins: i2c2-0 {
+               i2c-pins {
+                       pinmux = <GPIOMUX(3, GPOUT_LOW,
+                                            GPOEN_SYS_I2C2_CLK,
+                                            GPI_SYS_I2C2_CLK)>,
+                                <GPIOMUX(2, GPOUT_LOW,
+                                            GPOEN_SYS_I2C2_DATA,
+                                            GPI_SYS_I2C2_DATA)>;
+                       bias-disable; /* external pull-up */
+                       input-enable;
+                       input-schmitt-enable;
+               };
+       };
+
+       i2c5_pins: i2c5-0 {
+               i2c-pins {
+                       pinmux = <GPIOMUX(19, GPOUT_LOW,
+                                             GPOEN_SYS_I2C5_CLK,
+                                             GPI_SYS_I2C5_CLK)>,
+                                <GPIOMUX(20, GPOUT_LOW,
+                                             GPOEN_SYS_I2C5_DATA,
+                                             GPI_SYS_I2C5_DATA)>;
+                       bias-disable; /* external pull-up */
+                       input-enable;
+                       input-schmitt-enable;
+               };
+       };
+
+       i2c6_pins: i2c6-0 {
+               i2c-pins {
+                       pinmux = <GPIOMUX(16, GPOUT_LOW,
+                                             GPOEN_SYS_I2C6_CLK,
+                                             GPI_SYS_I2C6_CLK)>,
+                                <GPIOMUX(17, GPOUT_LOW,
+                                             GPOEN_SYS_I2C6_DATA,
+                                             GPI_SYS_I2C6_DATA)>;
+                       bias-disable; /* external pull-up */
+                       input-enable;
+                       input-schmitt-enable;
+               };
+       };
+
+       mmc0_pins: mmc0-pins {
+                mmc0-pins-rest {
+                       pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
+                                             GPOEN_ENABLE, GPI_NONE)>;
+                       bias-pull-up;
+                       drive-strength = <12>;
+                       input-disable;
+                       input-schmitt-disable;
+                       slew-rate = <0>;
+               };
+       };
+
+       mmc1_pins: mmc1-pins {
+               mmc1-pins0 {
+                       pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
+                                             GPOEN_ENABLE, GPI_NONE)>;
+                       bias-pull-up;
+                       drive-strength = <12>;
+                       input-disable;
+                       input-schmitt-disable;
+                       slew-rate = <0>;
+               };
+
+               mmc1-pins1 {
+                       pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
+                                            GPOEN_SYS_SDIO1_CMD, GPI_SYS_SDIO1_CMD)>,
+                               <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
+                                            GPOEN_SYS_SDIO1_DATA0, GPI_SYS_SDIO1_DATA0)>,
+                               <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
+                                            GPOEN_SYS_SDIO1_DATA1, GPI_SYS_SDIO1_DATA1)>,
+                               <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
+                                            GPOEN_SYS_SDIO1_DATA2, GPI_SYS_SDIO1_DATA2)>,
+                               <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
+                                            GPOEN_SYS_SDIO1_DATA3, GPI_SYS_SDIO1_DATA3)>;
+                       bias-pull-up;
+                       drive-strength = <12>;
+                       input-enable;
+                       input-schmitt-enable;
+                       slew-rate = <0>;
+               };
+       };
+};
+
+&mmc0 {
+       compatible = "snps,dw-mshc";
+       max-frequency = <100000000>;
+       bus-width = <8>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&mmc0_pins>;
+       cap-mmc-highspeed;
+       mmc-ddr-1_8v;
+       mmc-hs200-1_8v;
+       non-removable;
+       cap-mmc-hw-reset;
+       post-power-on-delay-ms = <200>;
+       status = "okay";
+
+};
+
+&mmc1 {
+       compatible = "snps,dw-mshc";
+       max-frequency = <100000000>;
+       bus-width = <4>;
+       pinctrl-names = "default";
+       pinctrl-0 = <&mmc1_pins>;
+       no-sdio;
+       no-mmc;
+       broken-cd;
+       cap-sd-highspeed;
+       post-power-on-delay-ms = <200>;
+       status = "okay";
+};
+
+&qspi {
+       spi-max-frequency = <250000000>;
+       status = "okay";
+
+       nor-flash@0 {
+               compatible = "jedec,spi-nor";
+               reg=<0>;
+               spi-max-frequency = <100000000>;
+               cdns,tshsl-ns = <1>;
+               cdns,tsd2d-ns = <1>;
+               cdns,tchsh-ns = <1>;
+               cdns,tslch-ns = <1>;
+       };
+};
+
+&syscrg {
+       assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
+                         <&syscrg JH7110_SYSCLK_BUS_ROOT>,
+                         <&syscrg JH7110_SYSCLK_PERH_ROOT>,
+                         <&syscrg JH7110_SYSCLK_QSPI_REF>;
+       assigned-clock-parents = <&syscrg JH7110_SYSCLK_PLL0_OUT>,
+                                <&syscrg JH7110_SYSCLK_PLL2_OUT>,
+                                <&syscrg JH7110_SYSCLK_PLL2_OUT>,
+                                <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
+       assigned-clock-rates = <0>, <0>, <0>, <0>;
+};
+
+&aoncrg {
+       assigned-clocks = <&aoncrg JH7110_AONCLK_APB_FUNC>;
+       assigned-clock-parents = <&osc>;
+       assigned-clock-rates = <0>;
+};