ARM: DRA7: Enable software leveling for dra7

Currently hw leveling is enabled by default on DRA7/72.
But the hardware team suggested to use sw leveling as hw leveling
is not characterized and seen some test case failures.
So enabling sw leveling on all DRA7 platforms.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 71c0cc8f2e440e0fbc72a77ae19e197cabf634b1..c8e9bc86e588c8dc3e54e255af7cabbabf7b6618 100644 (file)
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -242,46 +242,10 @@ static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
               __udelay(130);
 }
 
-static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
-{
-       struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
-
-       u32 fifo_reg;
-
-       fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_1);
-       writel(fifo_reg | 0x00000100,
-              &emif->emif_ddr_fifo_misaligned_clear_1);
-
-       fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_2);
-       writel(fifo_reg | 0x00000100,
-              &emif->emif_ddr_fifo_misaligned_clear_2);
-
-       /* Launch Full leveling */
-       writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
-
-       /* Wait till full leveling is complete */
-       readl(&emif->emif_rd_wr_lvl_ctl);
-             __udelay(130);
-
-       /* Read data eye leveling no of samples */
-       config_data_eye_leveling_samples(base);
-
-       /*
-        * Disable leveling. This is because if leveling is kept
-        * enabled, then PHY triggers a false leveling during
-        * EMIF-idle scenario which results in wrong delay
-        * values getting updated. After this the EMIF becomes
-        * unaccessible. So disable it after the first time
-        */
-       writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
-}
-
 static void ddr3_leveling(u32 base, const struct emif_regs *regs)
 {
        if (is_omap54xx())
                omap5_ddr3_leveling(base, regs);
-       else
-               dra7_ddr3_leveling(base, regs);
 }
 
 static void ddr3_init(u32 base, const struct emif_regs *regs)
@@ -1383,7 +1347,7 @@ void sdram_init(void)
        }
 
        if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
-           (!in_sdram && !warm_reset())) {
+           (!in_sdram && !warm_reset()) && (!is_dra7xx())) {
                if (emif1_enabled)
                        do_bug0039_workaround(EMIF1_BASE);
                if (emif2_enabled)

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index 4baca11d7a93d9ef0c85f3f3f32f6cc2ace246dc..ed89f85458dd86a6b9f06cbf7a1369ddeedfa4cd 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -556,7 +556,7 @@ const struct ctrl_ioregs ioregs_dra7xx_es1 = {
        .ctrl_ddrio_1 = 0x84210840,
        .ctrl_ddrio_2 = 0x84210000,
        .ctrl_emif_sdram_config_ext = 0x0001C1A7,
-       .ctrl_emif_sdram_config_ext_final = 0x000101A7,
+       .ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
        .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
 };
 

diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index e2ebab826232709a599d1d91e443f942ca7e660f..9105121ff60a04347c4bfd3b271ad625c0e10e1c 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -145,18 +145,18 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
        .sdram_tim1                     = 0xCCCF36B3,
        .sdram_tim2                     = 0x308F7FDA,
        .sdram_tim3                     = 0x027F88A8,
-       .read_idle_ctrl                 = 0x00050000,
+       .read_idle_ctrl                 = 0x00050001,
        .zq_config                      = 0x0007190B,
        .temp_alert_config              = 0x00000000,
-       .emif_ddr_phy_ctlr_1_init       = 0x0024400A,
-       .emif_ddr_phy_ctlr_1            = 0x0024400A,
+       .emif_ddr_phy_ctlr_1_init       = 0x0E24400A,
+       .emif_ddr_phy_ctlr_1            = 0x0E24400A,
        .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
-       .emif_ddr_ext_phy_ctrl_2        = 0x00B000B0,
-       .emif_ddr_ext_phy_ctrl_3        = 0x00B000B0,
-       .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
-       .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
+       .emif_ddr_ext_phy_ctrl_2        = 0x00BB00BB,
+       .emif_ddr_ext_phy_ctrl_3        = 0x00BB00BB,
+       .emif_ddr_ext_phy_ctrl_4        = 0x00BB00BB,
+       .emif_ddr_ext_phy_ctrl_5        = 0x00BB00BB,
        .emif_rd_wr_lvl_rmp_win         = 0x00000000,
-       .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+       .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
        .emif_rd_wr_lvl_ctl             = 0x00000000,
        .emif_rd_wr_exec_thresh         = 0x00000305
 };
@@ -169,18 +169,18 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
        .sdram_tim1                     = 0xCCCF36B3,
        .sdram_tim2                     = 0x308F7FDA,
        .sdram_tim3                     = 0x027F88A8,
-       .read_idle_ctrl                 = 0x00050000,
+       .read_idle_ctrl                 = 0x00050001,
        .zq_config                      = 0x0007190B,
        .temp_alert_config              = 0x00000000,
-       .emif_ddr_phy_ctlr_1_init       = 0x0024400A,
-       .emif_ddr_phy_ctlr_1            = 0x0024400A,
+       .emif_ddr_phy_ctlr_1_init       = 0x0E24400A,
+       .emif_ddr_phy_ctlr_1            = 0x0E24400A,
        .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
-       .emif_ddr_ext_phy_ctrl_2        = 0x00B000B0,
-       .emif_ddr_ext_phy_ctrl_3        = 0x00B000B0,
-       .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
-       .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
+       .emif_ddr_ext_phy_ctrl_2        = 0x00BB00BB,
+       .emif_ddr_ext_phy_ctrl_3        = 0x00BB00BB,
+       .emif_ddr_ext_phy_ctrl_4        = 0x00BB00BB,
+       .emif_ddr_ext_phy_ctrl_5        = 0x00BB00BB,
        .emif_rd_wr_lvl_rmp_win         = 0x00000000,
-       .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+       .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
        .emif_rd_wr_lvl_ctl             = 0x00000000,
        .emif_rd_wr_exec_thresh         = 0x00000305
 };
@@ -394,24 +394,24 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
 
 const u32
 dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
-       0x00B000B0,
-       0x00400040,
-       0x00400040,
-       0x00400040,
-       0x00400040,
-       0x00400040,
-       0x00800080,
-       0x00800080,
-       0x00800080,
-       0x00800080,
-       0x00800080,
+       0x00BB00BB,
+       0x00440044,
+       0x00440044,
+       0x00440044,
+       0x00440044,
+       0x00440044,
+       0x007F007F,
+       0x007F007F,
+       0x007F007F,
+       0x007F007F,
+       0x007F007F,
        0x00600060,
        0x00600060,
        0x00600060,
        0x00600060,
        0x00600060,
-       0x00800080,
-       0x00800080,
+       0x00000000,
+       0x00600020,
        0x40010080,
        0x08102040,
        0x0,
@@ -439,7 +439,7 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
        0x00600060,
        0x00600060,
        0x00600060,
-       0x0,
+       0x00000000,
        0x00600020,
        0x40010080,
        0x08102040,