clk: rockchip: rk3568: add more supported clk rates for sdmmc and emmc

SDHCI driver may attempt to set 26MHz clock, but clk_rk3568
will return error in this case. Apparently, SDHCI silently ignores the
error and as a result eMMC initialization fails.

Add 25 MHz and 26 MHz clk rates for sdmmc and emmc on rk3568 to fix that.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c
index d5e45e7602c7c1c7fe2e5738e6ae8b3e969b278b..99c195b3afe3d6edabe97b2f157f54dd6c1dc36e 100644 (file)
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -1442,6 +1442,7 @@ static ulong rk3568_sdmmc_set_clk(struct rk3568_clk_priv *priv,
        switch (rate) {
        case OSC_HZ:
        case 26 * MHz:
+       case 25 * MHz:
                src_clk = CLK_SDMMC_SEL_24M;
                break;
        case 400 * MHz:
@@ -1631,6 +1632,8 @@ static ulong rk3568_emmc_set_clk(struct rk3568_clk_priv *priv, ulong rate)
 
        switch (rate) {
        case OSC_HZ:
+       case 26 * MHz:
+       case 25 * MHz:
                src_clk = CCLK_EMMC_SEL_24M;
                break;
        case 52 * MHz: