]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
imx: mx6: add get_cpu_temp_grade to obtain cpu temperature grade from OTP
authorTim Harvey <tharvey@gateworks.com>
Mon, 18 May 2015 13:56:45 +0000 (06:56 -0700)
committerStefano Babic <sbabic@denx.de>
Tue, 19 May 2015 13:31:40 +0000 (15:31 +0200)
The MX6 has a temperature grade defined by OCOTP_MEM0[7:6] which is at 0x480
in the Fusemap Description Table in the reference manual. Return this value
as well as min/max temperature based on the value.

Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the
their Fusemap Description Table however Freescale has confirmed that these
eFUSE bits match the description within the IMX6DQRM and that they will
be added to the next revision of the respective reference manuals.

This has been tested with IMX6 Automative and Industrial parts.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
arch/arm/cpu/armv7/mx6/soc.c
arch/arm/include/asm/arch-mx6/sys_proto.h
include/imx_thermal.h

index f91b725b15c8b2f55bfd5cd64aac47fd888828fb..b21bd03a8aac99a50bbdf9b2be6f3b2fda4b9d60 100644 (file)
@@ -124,6 +124,44 @@ u32 get_cpu_speed_grade_hz(void)
        return 0;
 }
 
+/*
+ * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
+ * defines a 2-bit Temperature Grade
+ *
+ * return temperature grade and min/max temperature in celcius
+ */
+#define OCOTP_MEM0_TEMP_SHIFT          6
+
+u32 get_cpu_temp_grade(int *minc, int *maxc)
+{
+       struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+       struct fuse_bank *bank = &ocotp->bank[1];
+       struct fuse_bank1_regs *fuse =
+               (struct fuse_bank1_regs *)bank->fuse_regs;
+       uint32_t val;
+
+       val = readl(&fuse->mem0);
+       val >>= OCOTP_MEM0_TEMP_SHIFT;
+       val &= 0x3;
+
+       if (minc && maxc) {
+               if (val == TEMP_AUTOMOTIVE) {
+                       *minc = -40;
+                       *maxc = 125;
+               } else if (val == TEMP_INDUSTRIAL) {
+                       *minc = -40;
+                       *maxc = 105;
+               } else if (val == TEMP_EXTCOMMERCIAL) {
+                       *minc = -20;
+                       *maxc = 105;
+               } else {
+                       *minc = 0;
+                       *maxc = 95;
+               }
+       }
+       return val;
+}
+
 #ifdef CONFIG_REVISION_TAG
 u32 __weak get_board_rev(void)
 {
index a2cd0a9efff2731d996df9fcd404202629a61132..c5832912b4221f21ce9e958d15040a2dc9490f5a 100644 (file)
@@ -17,6 +17,7 @@
 u32 get_nr_cpus(void);
 u32 get_cpu_rev(void);
 u32 get_cpu_speed_grade_hz(void);
+u32 get_cpu_temp_grade(int *minc, int *maxc);
 
 /* returns MXC_CPU_ value */
 #define cpu_type(rev) (((rev) >> 12)&0xff)
index be1365288e5da5316932cd9e062515dc522f8831..8ce333cd56a0cff20a9a6fe07d85807416b7dcbc 100644 (file)
@@ -8,6 +8,12 @@
 #ifndef _IMX_THERMAL_H_
 #define _IMX_THERMAL_H_
 
+/* CPU Temperature Grades */
+#define TEMP_COMMERCIAL         0
+#define TEMP_EXTCOMMERCIAL      1
+#define TEMP_INDUSTRIAL         2
+#define TEMP_AUTOMOTIVE         3
+
 struct imx_thermal_plat {
        void *regs;
        int fuse_bank;