[PATCH] 44x: Fix problem with DDR controller setup (refresh rate)

This patch fixes a problem with an incorrect setup for the refresh
timer of the 44x DDR controller in the file cpu/ppc4xx/sdram.c

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c
index f06038e99833203d78befb5ffec4d39285d9b415..294b89cb2a20b59f9f3b11cc4fc73768d34b3a3d 100644 (file)
--- a/cpu/ppc4xx/sdram.c
+++ b/cpu/ppc4xx/sdram.c
@@ -380,7 +380,7 @@ long int initdram(int board_type)
                mtsdram(mem_b0cr, mb0cf[i].reg);
                mtsdram(mem_tr0, 0x41094012);
                mtsdram(mem_tr1, 0x80800800);   /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
-               mtsdram(mem_rtr, 0x7e000000);   /* Interval 15.20µs @ 133MHz PLB*/
+               mtsdram(mem_rtr, 0x04100000);   /* Interval 7.8µs @ 133MHz PLB  */
                mtsdram(mem_cfg1, 0x00000000);  /* Self-refresh exit, disable PM*/
                udelay(400);                    /* Delay 200 usecs (min)        */