mx31: make HSP clock for mx3fb driver available

This additionally updates mx31/generic.c by
- replacing __REG() macro accesses with readl() and writel()
- providing macros for PDR0 and PLL bit accesses

Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Anatolij Gustschin <agust@denx.de>

diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c
index c6def5df9b9250876459e4591a7eac40f2fc8b16..5524b232751e0c46a882f9b7bbd9d35bb75f7c3e 100644 (file)
--- a/arch/arm/cpu/arm1136/mx31/generic.c
+++ b/arch/arm/cpu/arm1136/mx31/generic.c
@@ -28,10 +28,10 @@
 
 static u32 mx31_decode_pll(u32 reg, u32 infreq)
 {
-       u32 mfi = (reg >> 10) & 0xf;
-       u32 mfn = reg & 0x3ff;
-       u32 mfd = (reg >> 16) & 0x3ff;
-       u32 pd =  (reg >> 26) & 0xf;
+       u32 mfi = GET_PLL_MFI(reg);
+       u32 mfn = GET_PLL_MFN(reg);
+       u32 mfd = GET_PLL_MFD(reg);
+       u32 pd =  GET_PLL_PD(reg);
 
        mfi = mfi <= 5 ? 5 : mfi;
        mfd += 1;
@@ -45,12 +45,12 @@ static u32 mx31_get_mpl_dpdgck_clk(void)
 {
        u32 infreq;
 
-       if ((__REG(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
+       if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
                infreq = CONFIG_MX31_CLK32 * 1024;
        else
                infreq = CONFIG_MX31_HCLK_FREQ;
 
-       return mx31_decode_pll(__REG(CCM_MPCTL), infreq);
+       return mx31_decode_pll(readl(CCM_MPCTL), infreq);
 }
 
 static u32 mx31_get_mcu_main_clk(void)
@@ -64,10 +64,21 @@ static u32 mx31_get_mcu_main_clk(void)
 static u32 mx31_get_ipg_clk(void)
 {
        u32 freq = mx31_get_mcu_main_clk();
-       u32 pdr0 = __REG(CCM_PDR0);
+       u32 pdr0 = readl(CCM_PDR0);
 
-       freq /= ((pdr0 >> 3) & 0x7) + 1;
-       freq /= ((pdr0 >> 6) & 0x3) + 1;
+       freq /= GET_PDR0_MAX_PODF(pdr0) + 1;
+       freq /= GET_PDR0_IPG_PODF(pdr0) + 1;
+
+       return freq;
+}
+
+/* hsp is the clock for the ipu */
+static u32 mx31_get_hsp_clk(void)
+{
+       u32 freq = mx31_get_mcu_main_clk();
+       u32 pdr0 = readl(CCM_PDR0);
+
+       freq /= GET_PDR0_HSP_PODF(pdr0) + 1;
 
        return freq;
 }
@@ -77,6 +88,7 @@ void mx31_dump_clocks(void)
        u32 cpufreq = mx31_get_mcu_main_clk();
        printf("mx31 cpu clock: %dMHz\n",cpufreq / 1000000);
        printf("ipg clock     : %dHz\n", mx31_get_ipg_clk());
+       printf("hsp clock     : %dHz\n", mx31_get_hsp_clk());
 }
 
 unsigned int mxc_get_clock(enum mxc_clock clk)
@@ -89,6 +101,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
        case MXC_CSPI_CLK:
        case MXC_UART_CLK:
                return mx31_get_ipg_clk();
+       case MXC_IPU_CLK:
+               return mx31_get_hsp_clk();
        }
        return -1;
 }
@@ -105,10 +119,10 @@ void mx31_gpio_mux(unsigned long mode)
        reg = IOMUXC_BASE + (mode & 0x1fc);
        shift = (~mode & 0x3) * 8;
 
-       tmp = __REG(reg);
+       tmp = readl(reg);
        tmp &= ~(0xff << shift);
        tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift;
-       __REG(reg) = tmp;
+       writel(tmp, reg);
 }
 
 void mx31_set_pad(enum iomux_pins pin, u32 config)
@@ -119,10 +133,10 @@ void mx31_set_pad(enum iomux_pins pin, u32 config)
        reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4;
        field = (pin + 2) % 3;
 
-       l = __REG(reg);
+       l = readl(reg);
        l &= ~(0x1ff << (field * 10));
        l |= config << (field * 10);
-       __REG(reg) = l;
+       writel(l, reg);
 
 }
 

diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h
index cc99a75e92a648be28ea49c6eded45d28fb4534c..2e3bce2c31295b4f7f36b41f80fb5a6cc94622cc 100644 (file)
--- a/arch/arm/include/asm/arch-mx31/clock.h
+++ b/arch/arm/include/asm/arch-mx31/clock.h
@@ -30,6 +30,7 @@ enum mxc_clock {
        MXC_IPG_PERCLK,
        MXC_CSPI_CLK,
        MXC_UART_CLK,
+       MXC_IPU_CLK
 };
 
 unsigned int mxc_get_clock(enum mxc_clock clk);

diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 0dcd9fe7eb62f3b0bedcf837a4fc73ce671e5363..f263e6bcfa3287db4335f9234d8bda7ef8c54777 100644 (file)
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -513,6 +513,20 @@ enum iomux_pins {
 #define PLL_MFI(x)             (((x) & 0xf) << 10)
 #define PLL_MFN(x)             (((x) & 0x3ff) << 0)
 
+#define GET_PDR0_CSI_PODF(x)   (((x) >> 23) & 0x1ff)
+#define GET_PDR0_PER_PODF(x)   (((x) >> 16) & 0x1f)
+#define GET_PDR0_HSP_PODF(x)   (((x) >> 11) & 0x7)
+#define GET_PDR0_NFC_PODF(x)   (((x) >> 8) & 0x7)
+#define GET_PDR0_IPG_PODF(x)   (((x) >> 6) & 0x3)
+#define GET_PDR0_MAX_PODF(x)   (((x) >> 3) & 0x7)
+#define GET_PDR0_MCU_PODF(x)   ((x) & 0x7)
+
+#define GET_PLL_PD(x)          (((x) >> 26) & 0xf)
+#define GET_PLL_MFD(x)         (((x) >> 16) & 0x3ff)
+#define GET_PLL_MFI(x)         (((x) >> 10) & 0xf)
+#define GET_PLL_MFN(x)         (((x) >> 0) & 0x3ff)
+
+
 #define WEIM_ESDCTL0   0xB8001000
 #define WEIM_ESDCFG0   0xB8001004
 #define WEIM_ESDCTL1   0xB8001008