ARM: dts: K3-am642-r5-sk: Enable Second CPSW port in R5/A53 SPL

Enable Second Ethernet port on which ROM support Ethboot.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts
index 71fcf61ff9fbd9ef8db3c439245caecb9b35ab02..3a17448ca0eb4f485bbfa6c0c9db15ea861d490a 100644 (file)
--- a/arch/arm/dts/k3-am642-r5-sk.dts
+++ b/arch/arm/dts/k3-am642-r5-sk.dts
@@ -7,6 +7,7 @@
 
 #include <dt-bindings/mux/ti-serdes.h>
 #include <dt-bindings/phy/phy.h>
+#include <dt-bindings/net/ti-dp83867.h>
 #include "k3-am642.dtsi"
 #include "k3-am64-sk-lp4-1333MTs.dtsi"
 #include "k3-am64-ddr.dtsi"
@@ -116,6 +117,47 @@
                        AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
                >;
        };
+
+       mdio1_pins_default: mdio1-pins-default {
+               pinctrl-single,pins = <
+                       AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
+                       AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
+               >;
+       };
+
+       rgmii1_pins_default: rgmii1-pins-default {
+               pinctrl-single,pins = <
+                       AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
+                       AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
+                       AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
+                       AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
+                       AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
+                       AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
+                       AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
+                       AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
+                       AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
+                       AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
+                       AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
+                       AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
+               >;
+       };
+
+       rgmii2_pins_default: rgmii2-pins-default {
+               pinctrl-single,pins = <
+                       AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
+                       AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
+                       AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
+                       AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
+                       AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
+                       AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
+                       AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
+                       AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
+                       AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
+                       AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
+                       AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
+                       AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
+               >;
+       };
 };
 
 &dmsc {
@@ -182,4 +224,35 @@
        phy-names = "cdns3,usb3-phy";
 };
 
+&cpsw3g {
+       pinctrl-names = "default";
+       pinctrl-0 = <&mdio1_pins_default
+                    &rgmii1_pins_default
+                    &rgmii2_pins_default>;
+};
+
+&cpsw_port1 {
+       phy-mode = "rgmii-rxid";
+       phy-handle = <&cpsw3g_phy0>;
+};
+
+&cpsw_port2 {
+       phy-mode = "rgmii-rxid";
+       phy-handle = <&cpsw3g_phy1>;
+};
+
+&cpsw3g_mdio {
+       cpsw3g_phy0: ethernet-phy@0 {
+               reg = <0>;
+               ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+               ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+       };
+
+       cpsw3g_phy1: ethernet-phy@1 {
+               reg = <1>;
+               ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+               ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+       };
+};
+
 #include "k3-am642-sk-u-boot.dtsi"

diff --git a/arch/arm/dts/k3-am642-sk-u-boot.dtsi b/arch/arm/dts/k3-am642-sk-u-boot.dtsi
index 95cf52c37fab27bf541eb3fb75b2ea275dc79f11..2f5cfaa04fd8a3e7e37cf58a6d1b44bf3840aff3 100644 (file)
--- a/arch/arm/dts/k3-am642-sk-u-boot.dtsi
+++ b/arch/arm/dts/k3-am642-sk-u-boot.dtsi
@@ -100,15 +100,53 @@
              <0x0 0x43000200 0x0 0x8>;
        reg-names = "cpsw_nuss", "mac_efuse";
        /delete-property/ ranges;
+       u-boot,dm-spl;
 
        cpsw-phy-sel@04044 {
                compatible = "ti,am64-phy-gmii-sel";
                reg = <0x0 0x43004044 0x0 0x8>;
+               u-boot,dm-spl;
+       };
+
+       ethernet-ports {
+               u-boot,dm-spl;
        };
 };
 
 &cpsw_port2 {
-       status = "disabled";
+       u-boot,dm-spl;
+};
+
+&cpsw_port1 {
+       u-boot,dm-spl;
+};
+
+&main_bcdma {
+       u-boot,dm-spl;
+};
+
+&main_pktdma {
+       u-boot,dm-spl;
+};
+
+&rgmii1_pins_default {
+       u-boot,dm-spl;
+};
+
+&rgmii2_pins_default {
+       u-boot,dm-spl;
+};
+
+&mdio1_pins_default {
+       u-boot,dm-spl;
+};
+
+&cpsw3g_phy0 {
+       u-boot,dm-spl;
+};
+
+&cpsw3g_phy1 {
+       u-boot,dm-spl;
 };
 
 &main_usb0_pins_default {