tegra: dts: Sync tegra20.dtsi with Linux v4.4

This file has changed quite a bit since it was set up. Sync it back with
Linux v4.4. Adjust the users slightly to cope with the changes:

- the host1x node is now called host1x@50000000
- we need a clocks node to provide the clk32k_in phandle
- active usb nodes need status = "okay"
- active i2c nodes need status = "okay"

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/dts/tegra20-colibri.dts b/arch/arm/dts/tegra20-colibri.dts
index f058d45c5ca8fcf2bb8ba68d0e1f1c49e777779b..2bed516f47ee4ab5488fcaa5f91ee5dc2abb67c3 100644 (file)
--- a/arch/arm/dts/tegra20-colibri.dts
+++ b/arch/arm/dts/tegra20-colibri.dts
@@ -20,7 +20,7 @@
                sdhci0 = "/sdhci@c8000600";
        };
 
-       host1x {
+       host1x@50000000 {
                status = "okay";
                dc@54200000 {
                        status = "okay";
@@ -32,16 +32,19 @@
        };
 
        usb@c5000000 {
+               statuc = "okay";
                dr_mode = "otg";
        };
 
        usb@c5004000 {
+               statuc = "okay";
                /* VBUS_LAN */
                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
                nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
        };
 
        usb@c5008000 {
+               statuc = "okay";
                /* USBH_PEN */
                nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
        };
@@ -88,6 +91,19 @@
                cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
        };
 
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clock@0 {
+                       compatible = "fixed-clock";
+                       reg=<0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+       };
+
        lcd_panel: panel {
                clock = <25175000>;
                xres = <640>;

diff --git a/arch/arm/dts/tegra20-harmony.dts b/arch/arm/dts/tegra20-harmony.dts
index e6e42295e216620e7ad28dbd3ad0245410de30b4..3eb9aa503ed84280c4b18884201f32973dd1dfce 100644 (file)
--- a/arch/arm/dts/tegra20-harmony.dts
+++ b/arch/arm/dts/tegra20-harmony.dts
@@ -21,7 +21,7 @@
                reg = <0x00000000 0x40000000>;
        };
 
-       host1x {
+       host1x@50000000 {
                status = "okay";
                dc@54200000 {
                        status = "okay";
@@ -46,30 +46,15 @@
                };
        };
 
-       i2c@7000c000 {
-               status = "disabled";
-       };
-
-       i2c@7000c400 {
-               status = "disabled";
-       };
-
-       i2c@7000c500 {
-               status = "disabled";
-       };
-
-       i2c@7000d000 {
-               status = "disabled";
-       };
-
-       usb@c5000000 {
-               status = "disabled";
-       };
-
        usb@c5004000 {
+               statuc = "okay";
                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) 0>;
        };
 
+       usb@c5008000 {
+               status = "okay";
+       };
+
        sdhci@c8000200 {
                status = "okay";
                cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
@@ -86,6 +71,19 @@
                bus-width = <8>;
        };
 
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clock@0 {
+                       compatible = "fixed-clock";
+                       reg=<0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+       };
+
        lcd_panel: panel {
                clock = <42430000>;
                xres = <1024>;

diff --git a/arch/arm/dts/tegra20-medcom-wide.dts b/arch/arm/dts/tegra20-medcom-wide.dts
index b6b57abdef94f9b2f79a7a44c860bab3919c8e3e..a4886bf7156889522314b9861a6a2c3deb55b2e9 100644 (file)
--- a/arch/arm/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/dts/tegra20-medcom-wide.dts
@@ -19,7 +19,7 @@
                reg = <0x00000000 0x20000000>;
        };
 
-       host1x {
+       host1x@50000000 {
                status = "okay";
 
                dc@54200000 {
@@ -36,28 +36,8 @@
                clock-frequency = <216000000>;
        };
 
-       i2c@7000c000 {
-               status = "disabled";
-       };
-
-       i2c@7000c400 {
-               status = "disabled";
-       };
-
-       i2c@7000c500 {
-               status = "disabled";
-       };
-
-       i2c@7000d000 {
-               status = "disabled";
-       };
-
-       usb@c5000000 {
-               status = "disabled";
-       };
-
-       usb@c5004000 {
-               status = "disabled";
+       usb@c5008000 {
+               status = "okay";
        };
 
        lcd_panel: panel {

diff --git a/arch/arm/dts/tegra20-paz00.dts b/arch/arm/dts/tegra20-paz00.dts
index 16381c3a4c78777e39812e205361797aee3d984b..f5edff13496d3c6f2b7ecf56135bf97fbf0f09dd 100644 (file)
--- a/arch/arm/dts/tegra20-paz00.dts
+++ b/arch/arm/dts/tegra20-paz00.dts
@@ -20,7 +20,7 @@
                reg = <0x00000000 0x20000000>;
        };
 
-       host1x {
+       host1x@50000000 {
                status = "okay";
                dc@54200000 {
                        status = "okay";
@@ -35,28 +35,8 @@
                clock-frequency = < 216000000 >;
        };
 
-       i2c@7000c000 {
-               status = "disabled";
-       };
-
-       i2c@7000c400 {
-               status = "disabled";
-       };
-
-       i2c@7000c500 {
-               status = "disabled";
-       };
-
-       i2c@7000d000 {
-               status = "disabled";
-       };
-
-       usb@c5000000 {
-               status = "disabled";
-       };
-
-       usb@c5004000 {
-               status = "disabled";
+       usb@c5008000 {
+               status = "okay";
        };
 
        sdhci@c8000000 {
@@ -72,6 +52,19 @@
                bus-width = <8>;
        };
 
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clock@0 {
+                       compatible = "fixed-clock";
+                       reg=<0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+       };
+
        lcd_panel: panel {
                /* PAZ00 has 1024x600 */
                clock = <54030000>;

diff --git a/arch/arm/dts/tegra20-plutux.dts b/arch/arm/dts/tegra20-plutux.dts
index e5562a9ca5279f19525ab51627a05d442813d975..7f57f1d4b573a37a32e822f100fedc3fa3c85541 100644 (file)
--- a/arch/arm/dts/tegra20-plutux.dts
+++ b/arch/arm/dts/tegra20-plutux.dts
@@ -38,12 +38,4 @@
        i2c@7000d000 {
                status = "disabled";
        };
-
-       usb@c5000000 {
-               status = "disabled";
-       };
-
-       usb@c5004000 {
-               status = "disabled";
-       };
 };

diff --git a/arch/arm/dts/tegra20-seaboard.dts b/arch/arm/dts/tegra20-seaboard.dts
index 10f399284ae189ca9bee5c5d438dba3c7085bebc..02ea64dc8a208a2a73eb0439a154424fa95db52f 100644 (file)
--- a/arch/arm/dts/tegra20-seaboard.dts
+++ b/arch/arm/dts/tegra20-seaboard.dts
@@ -31,7 +31,7 @@
                reg = < 0x00000000 0x40000000 >;
        };
 
-       host1x {
+       host1x@50000000 {
                status = "okay";
                dc@54200000 {
                        status = "okay";
@@ -44,6 +44,7 @@
 
        /* This is not used in U-Boot, but is expected to be in kernel .dts */
        i2c@7000d000 {
+               status = "okay";
                clock-frequency = <100000>;
                pmic@34 {
                        compatible = "ti,tps6586x";
@@ -75,18 +76,21 @@
        };
 
        i2c@7000c000 {
+               status = "okay";
                clock-frequency = <100000>;
        };
 
        i2c@7000c400 {
-               status = "disabled";
+               status = "okay";
        };
 
        i2c@7000c500 {
+               status = "okay";
                clock-frequency = <100000>;
        };
 
        kbc@7000e200 {
+               status = "okay";
                linux,keymap = <0x00020011 0x0003001f 0x0004001e 0x0005002c
                        0x000701d0 0x0107007d 0x02060064 0x02070038 0x03000006
                        0x03010005 0x03020013 0x03030012 0x03040021 0x03050020
@@ -114,6 +118,8 @@
        };
 
        emc@7000f400 {
+               #address-cells = <1>;
+               #size-cells = <0>;
                emc-table@190000 {
                        reg = < 190000 >;
                        compatible = "nvidia,tegra20-emc-table";
@@ -151,6 +157,7 @@
        };
 
        usb@c5000000 {
+               status = "okay";
                nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
                dr_mode = "otg";
        };
@@ -159,6 +166,10 @@
                status = "disabled";
        };
 
+       usb@c5008000 {
+               status = "okay";
+       };
+
        sdhci@c8000400 {
                status = "okay";
                cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
@@ -172,6 +183,19 @@
                bus-width = <8>;
        };
 
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clock@0 {
+                       compatible = "fixed-clock";
+                       reg=<0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+       };
+
        lcd_panel: panel {
                /* Seaboard has 1366x768 */
                clock = <70600000>;

diff --git a/arch/arm/dts/tegra20-tamonten.dtsi b/arch/arm/dts/tegra20-tamonten.dtsi
index 78449e613379dc12ebc8914fdd5f8957c8150ac0..f13ef4d05a841772506121e97f91f7aca31ebd67 100644 (file)
--- a/arch/arm/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/dts/tegra20-tamonten.dtsi
@@ -8,7 +8,7 @@
                reg = <0x00000000 0x20000000>;
        };
 
-       host1x {
+       host1x@50000000 {
                hdmi {
                        vdd-supply = <&hdmi_vdd_reg>;
                        pll-supply = <&hdmi_pll_reg>;
@@ -483,6 +483,19 @@
                status = "okay";
        };
 
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clock@0 {
+                       compatible = "fixed-clock";
+                       reg=<0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+       };
+
        regulators {
                compatible = "simple-bus";
 

diff --git a/arch/arm/dts/tegra20-tec.dts b/arch/arm/dts/tegra20-tec.dts
index 94ba6dc2d41d65e6e9c85873594ccefea979f54d..b16f10d410ff6b19e3d7369faf149e4f8fd437d6 100644 (file)
--- a/arch/arm/dts/tegra20-tec.dts
+++ b/arch/arm/dts/tegra20-tec.dts
@@ -19,7 +19,7 @@
                reg = <0x00000000 0x20000000>;
        };
 
-       host1x {
+       host1x@50000000 {
                status = "okay";
 
                dc@54200000 {
@@ -52,14 +52,6 @@
                status = "disabled";
        };
 
-       usb@c5000000 {
-               status = "disabled";
-       };
-
-       usb@c5004000 {
-               status = "disabled";
-       };
-
        lcd_panel: panel {
                clock = <33260000>;
                xres = <800>;

diff --git a/arch/arm/dts/tegra20-trimslice.dts b/arch/arm/dts/tegra20-trimslice.dts
index 27b118f212ad7bec41953dd6e2c18c8da8c431b9..db13ff965178dcedb0df08312493432ffc3cfdc4 100644 (file)
--- a/arch/arm/dts/tegra20-trimslice.dts
+++ b/arch/arm/dts/tegra20-trimslice.dts
@@ -26,27 +26,11 @@
                clock-frequency = <216000000>;
        };
 
-       i2c@7000c000 {
-               status = "disabled";
-       };
-
        spi@7000c380 {
                status = "okay";
                spi-max-frequency = <25000000>;
        };
 
-       i2c@7000c400 {
-               status = "disabled";
-       };
-
-       i2c@7000c500 {
-               status = "disabled";
-       };
-
-       i2c@7000d000 {
-               status = "disabled";
-       };
-
        pcie-controller@80003000 {
                status = "okay";
 
@@ -62,13 +46,10 @@
        };
 
        usb@c5000000 {
+               status = "okay";
                nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
        };
 
-       usb@c5004000 {
-               status = "disabled";
-       };
-
        sdhci@c8000000 {
                status = "okay";
                bus-width = <4>;
@@ -81,6 +62,19 @@
                bus-width = <4>;
        };
 
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clock@0 {
+                       compatible = "fixed-clock";
+                       reg=<0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+       };
+
        regulators {
                compatible = "simple-bus";
                #address-cells = <1>;

diff --git a/arch/arm/dts/tegra20-ventana.dts b/arch/arm/dts/tegra20-ventana.dts
index 939e567d1334f8de272f8a35d4cec7ba142783a6..bbbe8b7a89874580687218b55a5500a03a54a33b 100644 (file)
--- a/arch/arm/dts/tegra20-ventana.dts
+++ b/arch/arm/dts/tegra20-ventana.dts
@@ -20,7 +20,7 @@
                reg = <0x00000000 0x40000000>;
        };
 
-       host1x {
+       host1x@50000000 {
                status = "okay";
                dc@54200000 {
                        status = "okay";
@@ -35,28 +35,8 @@
                clock-frequency = < 216000000 >;
        };
 
-       i2c@7000c000 {
-               status = "disabled";
-       };
-
-       i2c@7000c400 {
-               status = "disabled";
-       };
-
-       i2c@7000c500 {
-               status = "disabled";
-       };
-
-       i2c@7000d000 {
-               status = "disabled";
-       };
-
-       usb@c5000000 {
-               status = "disabled";
-       };
-
-       usb@c5004000 {
-               status = "disabled";
+       usb@c5008000 {
+               status = "okay";
        };
 
        sdhci@c8000400 {
@@ -72,6 +52,19 @@
                bus-width = <8>;
        };
 
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clock@0 {
+                       compatible = "fixed-clock";
+                       reg=<0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+       };
+
        lcd_panel: panel {
                clock = <72072000>;
                xres = <1366>;

diff --git a/arch/arm/dts/tegra20-whistler.dts b/arch/arm/dts/tegra20-whistler.dts
index c4a28eb427deff1bb0c79ada0d1fa857f8acd3da..358c5824f7cc1b46b5e4991dca6c46228155f153 100644 (file)
--- a/arch/arm/dts/tegra20-whistler.dts
+++ b/arch/arm/dts/tegra20-whistler.dts
@@ -26,19 +26,8 @@
                clock-frequency = < 216000000 >;
        };
 
-       i2c@7000c000 {
-               status = "disabled";
-       };
-
-       i2c@7000c400 {
-               status = "disabled";
-       };
-
-       i2c@7000c500 {
-               status = "disabled";
-       };
-
        i2c@7000d000 {
+               status = "okay";
                clock-frequency = <100000>;
 
                pmic@3c {
@@ -56,12 +45,8 @@
                };
        };
 
-       usb@c5000000 {
-               status = "disabled";
-       };
-
-       usb@c5004000 {
-               status = "disabled";
+       usb@c5008000 {
+               status = "okay";
        };
 
        sdhci@c8000400 {
@@ -74,4 +59,18 @@
                status = "okay";
                bus-width = <8>;
        };
+
+       clocks {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               clk32k_in: clock@0 {
+                       compatible = "fixed-clock";
+                       reg=<0>;
+                       #clock-cells = <0>;
+                       clock-frequency = <32768>;
+               };
+       };
+
 };

diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index e68d7be4785f34cc2d642d84a90c6ee8cb9d11e8..5b14be4fc54d7113286108e0a87898da29828dbc 100644 (file)
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -1,72 +1,92 @@
 #include <dt-bindings/clock/tegra20-car.h>
 #include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #include "skeleton.dtsi"
 
 / {
        compatible = "nvidia,tegra20";
-       interrupt-parent = <&intc>;
+       interrupt-parent = <&lic>;
 
-       host1x {
+       host1x@50000000 {
                compatible = "nvidia,tegra20-host1x", "simple-bus";
                reg = <0x50000000 0x00024000>;
-               interrupts = <0 65 0x04   /* mpcore syncpt */
-                             0 67 0x04>; /* mpcore general */
-               status = "disabled";
+               interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
+                            <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
+               clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
+               resets = <&tegra_car 28>;
+               reset-names = "host1x";
 
                #address-cells = <1>;
                #size-cells = <1>;
 
                ranges = <0x54000000 0x54000000 0x04000000>;
 
-               /* video-encoding/decoding */
-               mpe {
+               mpe@54040000 {
+                       compatible = "nvidia,tegra20-mpe";
                        reg = <0x54040000 0x00040000>;
-                       interrupts = <0 68 0x04>;
-                       status = "disabled";
+                       interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&tegra_car TEGRA20_CLK_MPE>;
+                       resets = <&tegra_car 60>;
+                       reset-names = "mpe";
                };
 
-               /* video input */
-               vi {
+               vi@54080000 {
+                       compatible = "nvidia,tegra20-vi";
                        reg = <0x54080000 0x00040000>;
-                       interrupts = <0 69 0x04>;
-                       status = "disabled";
+                       interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&tegra_car TEGRA20_CLK_VI>;
+                       resets = <&tegra_car 20>;
+                       reset-names = "vi";
                };
 
-               /* EPP */
-               epp {
+               epp@540c0000 {
+                       compatible = "nvidia,tegra20-epp";
                        reg = <0x540c0000 0x00040000>;
-                       interrupts = <0 70 0x04>;
-                       status = "disabled";
+                       interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&tegra_car TEGRA20_CLK_EPP>;
+                       resets = <&tegra_car 19>;
+                       reset-names = "epp";
                };
 
-               /* ISP */
-               isp {
+               isp@54100000 {
+                       compatible = "nvidia,tegra20-isp";
                        reg = <0x54100000 0x00040000>;
-                       interrupts = <0 71 0x04>;
-                       status = "disabled";
+                       interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&tegra_car TEGRA20_CLK_ISP>;
+                       resets = <&tegra_car 23>;
+                       reset-names = "isp";
                };
 
-               /* 2D engine */
-               gr2d {
+               gr2d@54140000 {
+                       compatible = "nvidia,tegra20-gr2d";
                        reg = <0x54140000 0x00040000>;
-                       interrupts = <0 72 0x04>;
-                       status = "disabled";
+                       interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&tegra_car TEGRA20_CLK_GR2D>;
+                       resets = <&tegra_car 21>;
+                       reset-names = "2d";
                };
 
-               /* 3D engine */
-               gr3d {
+               gr3d@54180000 {
+                       compatible = "nvidia,tegra20-gr3d";
                        reg = <0x54180000 0x00040000>;
-                       status = "disabled";
+                       clocks = <&tegra_car TEGRA20_CLK_GR3D>;
+                       resets = <&tegra_car 24>;
+                       reset-names = "3d";
                };
 
-               /* display controllers */
                dc@54200000 {
                        compatible = "nvidia,tegra20-dc";
                        reg = <0x54200000 0x00040000>;
-                       interrupts = <0 73 0x04>;
-                       status = "disabled";
+                       interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&tegra_car TEGRA20_CLK_DISP1>,
+                                <&tegra_car TEGRA20_CLK_PLL_P>;
+                       clock-names = "dc", "parent";
+                       resets = <&tegra_car 27>;
+                       reset-names = "dc";
+
+                       nvidia,head = <0>;
 
                        rgb {
                                status = "disabled";
@@ -76,69 +96,138 @@
                dc@54240000 {
                        compatible = "nvidia,tegra20-dc";
                        reg = <0x54240000 0x00040000>;
-                       interrupts = <0 74 0x04>;
-                       status = "disabled";
+                       interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&tegra_car TEGRA20_CLK_DISP2>,
+                                <&tegra_car TEGRA20_CLK_PLL_P>;
+                       clock-names = "dc", "parent";
+                       resets = <&tegra_car 26>;
+                       reset-names = "dc";
+
+                       nvidia,head = <1>;
 
                        rgb {
                                status = "disabled";
                        };
                };
 
-               /* outputs */
-               hdmi {
+               hdmi@54280000 {
                        compatible = "nvidia,tegra20-hdmi";
                        reg = <0x54280000 0x00040000>;
-                       interrupts = <0 75 0x04>;
+                       interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&tegra_car TEGRA20_CLK_HDMI>,
+                                <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
+                       clock-names = "hdmi", "parent";
+                       resets = <&tegra_car 51>;
+                       reset-names = "hdmi";
                        status = "disabled";
                };
 
-               tvo {
+               tvo@542c0000 {
                        compatible = "nvidia,tegra20-tvo";
                        reg = <0x542c0000 0x00040000>;
-                       interrupts = <0 76 0x04>;
+                       interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&tegra_car TEGRA20_CLK_TVO>;
                        status = "disabled";
                };
 
-               dsi {
+               dsi@54300000 {
                        compatible = "nvidia,tegra20-dsi";
                        reg = <0x54300000 0x00040000>;
+                       clocks = <&tegra_car TEGRA20_CLK_DSI>;
+                       resets = <&tegra_car 48>;
+                       reset-names = "dsi";
                        status = "disabled";
                };
        };
 
+       timer@50040600 {
+               compatible = "arm,cortex-a9-twd-timer";
+               interrupt-parent = <&intc>;
+               reg = <0x50040600 0x20>;
+               interrupts = <GIC_PPI 13
+                       (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+               clocks = <&tegra_car TEGRA20_CLK_TWD>;
+       };
+
        intc: interrupt-controller@50041000 {
-               compatible = "nvidia,tegra20-gic";
+               compatible = "arm,cortex-a9-gic";
+               reg = <0x50041000 0x1000
+                      0x50040100 0x0100>;
                interrupt-controller;
-               #interrupt-cells = <1>;
-               reg = < 0x50041000 0x1000 >,
-                     < 0x50040100 0x0100 >;
+               #interrupt-cells = <3>;
+               interrupt-parent = <&intc>;
+       };
+
+       cache-controller@50043000 {
+               compatible = "arm,pl310-cache";
+               reg = <0x50043000 0x1000>;
+               arm,data-latency = <5 5 2>;
+               arm,tag-latency = <4 4 2>;
+               cache-unified;
+               cache-level = <2>;
+       };
+
+       lic: interrupt-controller@60004000 {
+               compatible = "nvidia,tegra20-ictlr";
+               reg = <0x60004000 0x100>,
+                     <0x60004100 0x50>,
+                     <0x60004200 0x50>,
+                     <0x60004300 0x50>;
+               interrupt-controller;
+               #interrupt-cells = <3>;
+               interrupt-parent = <&intc>;
+       };
+
+       timer@60005000 {
+               compatible = "nvidia,tegra20-timer";
+               reg = <0x60005000 0x60>;
+               interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA20_CLK_TIMER>;
        };
 
        tegra_car: clock@60006000 {
                compatible = "nvidia,tegra20-car";
                reg = <0x60006000 0x1000>;
                #clock-cells = <1>;
+               #reset-cells = <1>;
+       };
+
+       flow-controller@60007000 {
+               compatible = "nvidia,tegra20-flowctrl";
+               reg = <0x60007000 0x1000>;
        };
 
-       apbdma: dma {
+       apbdma: dma@6000a000 {
                compatible = "nvidia,tegra20-apbdma";
                reg = <0x6000a000 0x1200>;
-               interrupts = <0 104 0x04
-                             0 105 0x04
-                             0 106 0x04
-                             0 107 0x04
-                             0 108 0x04
-                             0 109 0x04
-                             0 110 0x04
-                             0 111 0x04
-                             0 112 0x04
-                             0 113 0x04
-                             0 114 0x04
-                             0 115 0x04
-                             0 116 0x04
-                             0 117 0x04
-                             0 118 0x04
-                             0 119 0x04>;
+               interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
+               resets = <&tegra_car 34>;
+               reset-names = "dma";
+               #dma-cells = <1>;
+       };
+
+       ahb@6000c000 {
+               compatible = "nvidia,tegra20-ahb";
+               reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */
        };
 
        gpio: gpio@6000d000 {
@@ -155,41 +244,73 @@
                gpio-controller;
                #interrupt-cells = <2>;
                interrupt-controller;
+               /*
+               gpio-ranges = <&pinmux 0 0 224>;
+               */
+       };
+
+       apbmisc@70000800 {
+               compatible = "nvidia,tegra20-apbmisc";
+               reg = <0x70000800 0x64   /* Chip revision */
+                      0x70000008 0x04>; /* Strapping options */
        };
 
-       pinmux: pinmux@70000000 {
+       pinmux: pinmux@70000014 {
                compatible = "nvidia,tegra20-pinmux";
-               reg = < 0x70000014 0x10    /* Tri-state registers */
-                       0x70000080 0x20    /* Mux registers */
-                       0x700000a0 0x14    /* Pull-up/down registers */
-                       0x70000868 0xa8 >; /* Pad control registers */
+               reg = <0x70000014 0x10   /* Tri-state registers */
+                      0x70000080 0x20   /* Mux registers */
+                      0x700000a0 0x14   /* Pull-up/down registers */
+                      0x70000868 0xa8>; /* Pad control registers */
        };
 
        das@70000c00 {
-               #address-cells = <1>;
-               #size-cells = <0>;
                compatible = "nvidia,tegra20-das";
                reg = <0x70000c00 0x80>;
        };
 
-       i2s@70002800 {
-               #address-cells = <1>;
-               #size-cells = <0>;
+       tegra_ac97: ac97@70002000 {
+               compatible = "nvidia,tegra20-ac97";
+               reg = <0x70002000 0x200>;
+               interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA20_CLK_AC97>;
+               resets = <&tegra_car 3>;
+               reset-names = "ac97";
+               dmas = <&apbdma 12>, <&apbdma 12>;
+               dma-names = "rx", "tx";
+               status = "disabled";
+       };
+
+       tegra_i2s1: i2s@70002800 {
                compatible = "nvidia,tegra20-i2s";
                reg = <0x70002800 0x200>;
-               interrupts = < 45 >;
-               dma-channel = < 2 >;
+               interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA20_CLK_I2S1>;
+               resets = <&tegra_car 11>;
+               reset-names = "i2s";
+               dmas = <&apbdma 2>, <&apbdma 2>;
+               dma-names = "rx", "tx";
+               status = "disabled";
        };
 
-       i2s@70002a00 {
-               #address-cells = <1>;
-               #size-cells = <0>;
+       tegra_i2s2: i2s@70002a00 {
                compatible = "nvidia,tegra20-i2s";
                reg = <0x70002a00 0x200>;
-               interrupts = < 35 >;
-               dma-channel = < 1 >;
+               interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA20_CLK_I2S2>;
+               resets = <&tegra_car 18>;
+               reset-names = "i2s";
+               dmas = <&apbdma 1>, <&apbdma 1>;
+               dma-names = "rx", "tx";
+               status = "disabled";
        };
 
+       /*
+        * There are two serial driver i.e. 8250 based simple serial
+        * driver and APB DMA based serial driver for higher baudrate
+        * and performace. To enable the 8250 based driver, the compatible
+        * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
+        * driver, the comptible is "nvidia,tegra20-hsuart".
+        */
        uarta: serial@70006000 {
                compatible = "nvidia,tegra20-uart";
                reg = <0x70006000 0x40>;
@@ -266,58 +387,95 @@
                compatible = "nvidia,tegra20-pwm";
                reg = <0x7000a000 0x100>;
                #pwm-cells = <2>;
+               clocks = <&tegra_car TEGRA20_CLK_PWM>;
+               resets = <&tegra_car 17>;
+               reset-names = "pwm";
+               status = "disabled";
+       };
+
+       rtc@7000e000 {
+               compatible = "nvidia,tegra20-rtc";
+               reg = <0x7000e000 0x100>;
+               interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA20_CLK_RTC>;
        };
 
        i2c@7000c000 {
+               compatible = "nvidia,tegra20-i2c";
+               reg = <0x7000c000 0x100>;
+               interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-               compatible = "nvidia,tegra20-i2c";
-               reg = <0x7000C000 0x100>;
-               interrupts = < 70 >;
-               /* PERIPH_ID_I2C1, PLL_P_OUT3 */
-               clocks = <&tegra_car 12>, <&tegra_car 124>;
+               clocks = <&tegra_car TEGRA20_CLK_I2C1>,
+                        <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
+               clock-names = "div-clk", "fast-clk";
+               resets = <&tegra_car 12>;
+               reset-names = "i2c";
+               dmas = <&apbdma 21>, <&apbdma 21>;
+               dma-names = "rx", "tx";
+               status = "disabled";
        };
 
        spi@7000c380 {
                compatible = "nvidia,tegra20-sflash";
                reg = <0x7000c380 0x80>;
-               interrupts = <0 39 0x04>;
-               nvidia,dma-request-selector = <&apbdma 11>;
+               interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
+               clocks = <&tegra_car TEGRA20_CLK_SPI>;
+               resets = <&tegra_car 43>;
+               reset-names = "spi";
+               dmas = <&apbdma 11>, <&apbdma 11>;
+               dma-names = "rx", "tx";
                status = "disabled";
-               /* PERIPH_ID_SPI1, PLLP_OUT0 */
-               clocks = <&tegra_car 43>;
        };
 
        i2c@7000c400 {
+               compatible = "nvidia,tegra20-i2c";
+               reg = <0x7000c400 0x100>;
+               interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-               compatible = "nvidia,tegra20-i2c";
-               reg = <0x7000C400 0x100>;
-               interrupts = < 116 >;
-               /* PERIPH_ID_I2C2, PLL_P_OUT3 */
-               clocks = <&tegra_car 54>, <&tegra_car 124>;
+               clocks = <&tegra_car TEGRA20_CLK_I2C2>,
+                        <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
+               clock-names = "div-clk", "fast-clk";
+               resets = <&tegra_car 54>;
+               reset-names = "i2c";
+               dmas = <&apbdma 22>, <&apbdma 22>;
+               dma-names = "rx", "tx";
+               status = "disabled";
        };
 
        i2c@7000c500 {
+               compatible = "nvidia,tegra20-i2c";
+               reg = <0x7000c500 0x100>;
+               interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-               compatible = "nvidia,tegra20-i2c";
-               reg = <0x7000C500 0x100>;
-               interrupts = < 124 >;
-               /* PERIPH_ID_I2C3, PLL_P_OUT3 */
-               clocks = <&tegra_car 67>, <&tegra_car 124>;
+               clocks = <&tegra_car TEGRA20_CLK_I2C3>,
+                        <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
+               clock-names = "div-clk", "fast-clk";
+               resets = <&tegra_car 67>;
+               reset-names = "i2c";
+               dmas = <&apbdma 23>, <&apbdma 23>;
+               dma-names = "rx", "tx";
+               status = "disabled";
        };
 
        i2c@7000d000 {
+               compatible = "nvidia,tegra20-i2c-dvc";
+               reg = <0x7000d000 0x200>;
+               interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-               compatible = "nvidia,tegra20-i2c-dvc";
-               reg = <0x7000D000 0x200>;
-               interrupts = < 85 >;
-               /* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */
-               clocks = <&tegra_car 47>, <&tegra_car 124>;
+               clocks = <&tegra_car TEGRA20_CLK_DVC>,
+                        <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
+               clock-names = "div-clk", "fast-clk";
+               resets = <&tegra_car 47>;
+               reset-names = "i2c";
+               dmas = <&apbdma 24>, <&apbdma 24>;
+               dma-names = "rx", "tx";
+               status = "disabled";
        };
 
        spi@7000d400 {
@@ -376,17 +534,50 @@
                status = "disabled";
        };
 
-
        kbc@7000e200 {
                compatible = "nvidia,tegra20-kbc";
-               reg = <0x7000e200 0x0078>;
+               reg = <0x7000e200 0x100>;
+               interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA20_CLK_KBC>;
+               resets = <&tegra_car 36>;
+               reset-names = "kbc";
+               status = "disabled";
        };
 
-       emc@7000f400 {
-               #address-cells = < 1 >;
-               #size-cells = < 0 >;
+       pmc@7000e400 {
+               compatible = "nvidia,tegra20-pmc";
+               reg = <0x7000e400 0x400>;
+               clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
+               clock-names = "pclk", "clk32k_in";
+       };
+
+       memory-controller@7000f000 {
+               compatible = "nvidia,tegra20-mc";
+               reg = <0x7000f000 0x024
+                      0x7000f03c 0x3c4>;
+               interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+       };
+
+       iommu@7000f024 {
+               compatible = "nvidia,tegra20-gart";
+               reg = <0x7000f024 0x00000018    /* controller registers */
+                      0x58000000 0x02000000>;  /* GART aperture */
+       };
+
+       memory-controller@7000f400 {
                compatible = "nvidia,tegra20-emc";
                reg = <0x7000f400 0x200>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+       };
+
+       fuse@7000f800 {
+               compatible = "nvidia,tegra20-efuse";
+               reg = <0x7000f800 0x400>;
+               clocks = <&tegra_car TEGRA20_CLK_FUSE>;
+               clock-names = "fuse";
+               resets = <&tegra_car 39>;
+               reset-names = "fuse";
        };
 
        pcie-controller@80003000 {
@@ -416,9 +607,12 @@
 
                clocks = <&tegra_car TEGRA20_CLK_PEX>,
                         <&tegra_car TEGRA20_CLK_AFI>,
-                        <&tegra_car TEGRA20_CLK_PCIE_XCLK>,
                         <&tegra_car TEGRA20_CLK_PLL_E>;
-               clock-names = "pex", "afi", "pcie_xclk", "pll_e";
+               clock-names = "pex", "afi", "pll_e";
+               resets = <&tegra_car 70>,
+                        <&tegra_car 72>,
+                        <&tegra_car 74>;
+               reset-names = "pex", "afi", "pcie_x";
                status = "disabled";
 
                pci@1,0 {
@@ -451,57 +645,158 @@
        usb@c5000000 {
                compatible = "nvidia,tegra20-ehci", "usb-ehci";
                reg = <0xc5000000 0x4000>;
-               interrupts = < 52 >;
+               interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
                phy_type = "utmi";
-               clocks = <&tegra_car 22>;       /* PERIPH_ID_USBD */
                nvidia,has-legacy-mode;
+               clocks = <&tegra_car TEGRA20_CLK_USBD>;
+               resets = <&tegra_car 22>;
+               reset-names = "usb";
+               nvidia,needs-double-reset;
+               nvidia,phy = <&phy1>;
+               status = "disabled";
+       };
+
+       phy1: usb-phy@c5000000 {
+               compatible = "nvidia,tegra20-usb-phy";
+               reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
+               phy_type = "utmi";
+               clocks = <&tegra_car TEGRA20_CLK_USBD>,
+                        <&tegra_car TEGRA20_CLK_PLL_U>,
+                        <&tegra_car TEGRA20_CLK_CLK_M>,
+                        <&tegra_car TEGRA20_CLK_USBD>;
+               clock-names = "reg", "pll_u", "timer", "utmi-pads";
+               resets = <&tegra_car 22>, <&tegra_car 22>;
+               reset-names = "usb", "utmi-pads";
+               nvidia,has-legacy-mode;
+               nvidia,hssync-start-delay = <9>;
+               nvidia,idle-wait-delay = <17>;
+               nvidia,elastic-limit = <16>;
+               nvidia,term-range-adj = <6>;
+               nvidia,xcvr-setup = <9>;
+               nvidia,xcvr-lsfslew = <1>;
+               nvidia,xcvr-lsrslew = <1>;
+               nvidia,has-utmi-pad-registers;
+               status = "disabled";
        };
 
        usb@c5004000 {
                compatible = "nvidia,tegra20-ehci", "usb-ehci";
                reg = <0xc5004000 0x4000>;
-               interrupts = < 53 >;
+               interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+               phy_type = "ulpi";
+               clocks = <&tegra_car TEGRA20_CLK_USB2>;
+               resets = <&tegra_car 58>;
+               reset-names = "usb";
+               nvidia,phy = <&phy2>;
+               status = "disabled";
+       };
+
+       phy2: usb-phy@c5004000 {
+               compatible = "nvidia,tegra20-usb-phy";
+               reg = <0xc5004000 0x4000>;
                phy_type = "ulpi";
-               clocks = <&tegra_car 58>;       /* PERIPH_ID_USB2 */
+               clocks = <&tegra_car TEGRA20_CLK_USB2>,
+                        <&tegra_car TEGRA20_CLK_PLL_U>,
+                        <&tegra_car TEGRA20_CLK_CDEV2>;
+               clock-names = "reg", "pll_u", "ulpi-link";
+               resets = <&tegra_car 58>, <&tegra_car 22>;
+               reset-names = "usb", "utmi-pads";
+               status = "disabled";
        };
 
        usb@c5008000 {
                compatible = "nvidia,tegra20-ehci", "usb-ehci";
                reg = <0xc5008000 0x4000>;
-               interrupts = < 129 >;
+               interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+               phy_type = "utmi";
+               clocks = <&tegra_car TEGRA20_CLK_USB3>;
+               resets = <&tegra_car 59>;
+               reset-names = "usb";
+               nvidia,phy = <&phy3>;
+               status = "disabled";
+       };
+
+       phy3: usb-phy@c5008000 {
+               compatible = "nvidia,tegra20-usb-phy";
+               reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
                phy_type = "utmi";
-               clocks = <&tegra_car 59>;       /* PERIPH_ID_USB3 */
+               clocks = <&tegra_car TEGRA20_CLK_USB3>,
+                        <&tegra_car TEGRA20_CLK_PLL_U>,
+                        <&tegra_car TEGRA20_CLK_CLK_M>,
+                        <&tegra_car TEGRA20_CLK_USBD>;
+               clock-names = "reg", "pll_u", "timer", "utmi-pads";
+               resets = <&tegra_car 59>, <&tegra_car 22>;
+               reset-names = "usb", "utmi-pads";
+               nvidia,hssync-start-delay = <9>;
+               nvidia,idle-wait-delay = <17>;
+               nvidia,elastic-limit = <16>;
+               nvidia,term-range-adj = <6>;
+               nvidia,xcvr-setup = <9>;
+               nvidia,xcvr-lsfslew = <2>;
+               nvidia,xcvr-lsrslew = <2>;
+               status = "disabled";
        };
 
        sdhci@c8000000 {
                compatible = "nvidia,tegra20-sdhci";
                reg = <0xc8000000 0x200>;
-               interrupts = <0 14 0x04>;
-               clocks = <&tegra_car 14>;
+               interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
+               resets = <&tegra_car 14>;
+               reset-names = "sdhci";
                status = "disabled";
        };
 
        sdhci@c8000200 {
                compatible = "nvidia,tegra20-sdhci";
                reg = <0xc8000200 0x200>;
-               interrupts = <0 15 0x04>;
-               clocks = <&tegra_car 9>;
+               interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
+               resets = <&tegra_car 9>;
+               reset-names = "sdhci";
                status = "disabled";
        };
 
        sdhci@c8000400 {
                compatible = "nvidia,tegra20-sdhci";
                reg = <0xc8000400 0x200>;
-               interrupts = <0 19 0x04>;
-               clocks = <&tegra_car 69>;
+               interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
+               resets = <&tegra_car 69>;
+               reset-names = "sdhci";
                status = "disabled";
        };
 
        sdhci@c8000600 {
                compatible = "nvidia,tegra20-sdhci";
                reg = <0xc8000600 0x200>;
-               interrupts = <0 31 0x04>;
-               clocks = <&tegra_car 15>;
+               interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
+               resets = <&tegra_car 15>;
+               reset-names = "sdhci";
                status = "disabled";
        };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       reg = <0>;
+               };
+
+               cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a9";
+                       reg = <1>;
+               };
+       };
+
+       pmu {
+               compatible = "arm,cortex-a9-pmu";
+               interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+       };
 };