sunxi: H3/A64: fix non-ODT setting

According to Jens disabling the on-die-termination should set bit 5,
not bit 1 in the respective register. Fix this.

Reported-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>

diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c b/arch/arm/mach-sunxi/dram_sun8i_h3.c
index fe9cf9a181b392782a7a932c62b900e19c9865e6..1311edaf325b69a358275dc9687bc991864b0793 100644 (file)
--- a/arch/arm/mach-sunxi/dram_sun8i_h3.c
+++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c
@@ -414,6 +414,11 @@ static void mctl_sys_init(uint16_t socid, struct dram_para *para)
        udelay(500);
 }
 
+/* These are more guessed based on some Allwinner code. */
+#define DX_GCR_ODT_DYNAMIC     (0x0 << 4)
+#define DX_GCR_ODT_ALWAYS_ON   (0x1 << 4)
+#define DX_GCR_ODT_OFF         (0x2 << 4)
+
 static int mctl_channel_init(uint16_t socid, struct dram_para *para)
 {
        struct sunxi_mctl_com_reg * const mctl_com =
@@ -443,7 +448,8 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para)
                clrsetbits_le32(&mctl_ctl->dx[i].gcr, (0x3 << 4) |
                                (0x1 << 1) | (0x3 << 2) | (0x3 << 12) |
                                (0x3 << 14),
-                               IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x2);
+                               IS_ENABLED(CONFIG_DRAM_ODT_EN) ?
+                                       DX_GCR_ODT_DYNAMIC : DX_GCR_ODT_OFF);
 
        /* AC PDR should always ON */
        setbits_le32(&mctl_ctl->aciocr, 0x1 << 1);