ppc4xx: Update AMCC Makalu for board rev 1.1

This patch adds changes needed for Makalu rev 1.1:

- Enable 2nd DDR2 bank resulting in 256MByte of SDRAM
- Enable 2nd ethernet port EMAC1
- Use generic GPIO configuration framework (CFG_4xx_GPIO_TABLE)
- Reset PCIe ports via GPIO upon bootup

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/board/amcc/makalu/init.S b/board/amcc/makalu/init.S
index 806f5fdee2ea1f48d8d1274347571dc0e4b6215a..57c1774e028bb7de6583347b3c7bb2996d777252 100644 (file)
--- a/board/amcc/makalu/init.S
+++ b/board/amcc/makalu/init.S
@@ -54,14 +54,8 @@ ext_bus_cntlr_init:
        /* base=00000000, size=128MByte (5), mode=2 (n*10*4) */
        mtsdram_as(SDRAM_MB0CF, 0x00005201);
 
-       /* SET SDRAM_MB1CF - Not enabled */
-       mtsdram_as(SDRAM_MB1CF, 0x00000000);
-
-       /* SET SDRAM_MB2CF  - Not enabled */
-       mtsdram_as(SDRAM_MB2CF, 0x00000000);
-
-       /* SET SDRAM_MB3CF  - Not enabled */
-       mtsdram_as(SDRAM_MB3CF, 0x00000000);
+       /* base=08000000, size=128MByte (5), mode=2 (n*10*4) */
+       mtsdram_as(SDRAM_MB1CF, (0x08000000 >> 3) | 0x5201);
 
        /* SDRAM_CLKTR: Adv Addr clock by 90 deg */
        mtsdram_as(SDRAM_CLKTR,0x80000000);

diff --git a/board/amcc/makalu/makalu.c b/board/amcc/makalu/makalu.c
index 3b4a9c15477b6163862b79673f954c51c57af63e..b7933a056d1be76e198ed4116c7b52b5965a5735 100644 (file)
--- a/board/amcc/makalu/makalu.c
+++ b/board/amcc/makalu/makalu.c
@@ -26,7 +26,8 @@
 #include <ppc405.h>
 #include <libfdt.h>
 #include <asm/processor.h>
-#include <asm-ppc/io.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
 
 #if defined(CONFIG_PCI)
 #include <pci.h>
@@ -189,6 +190,11 @@ int board_early_init_f (void)
         */
        mtsdr(SDR0_SRST, 0);
 
+       /* Reset PCIe slots */
+       gpio_write_bit(CFG_GPIO_PCIE_RST, 0);
+       udelay(100);
+       gpio_write_bit(CFG_GPIO_PCIE_RST, 1);
+
        return 0;
 }
 
@@ -239,45 +245,6 @@ int pci_pre_init(struct pci_controller * hose )
 }
 #endif  /* defined(CONFIG_PCI) */
 
-/*************************************************************************
- *  pci_target_init
- *
- *      The bootstrap configuration provides default settings for the pci
- *      inbound map (PIM). But the bootstrap config choices are limited and
- *      may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
-       /*-------------------------------------------------------------------+
-        * Disable everything
-        *-------------------------------------------------------------------*/
-       out32r( PCIX0_PIM0SA, 0 ); /* disable */
-       out32r( PCIX0_PIM1SA, 0 ); /* disable */
-       out32r( PCIX0_PIM2SA, 0 ); /* disable */
-       out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
-
-       /*-------------------------------------------------------------------+
-        * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
-        * strapping options to not support sizes such as 128/256 MB.
-        *-------------------------------------------------------------------*/
-       out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
-       out32r( PCIX0_PIM0LAH, 0 );
-       out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-
-       out32r( PCIX0_BAR0, 0 );
-
-       /*-------------------------------------------------------------------+
-        * Program the board's subsystem id/vendor id
-        *-------------------------------------------------------------------*/
-       out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
-       out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
-
-       out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
-}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
-
 #ifdef CONFIG_PCI
 static struct pci_controller pcie_hose[2] = {{0},{0}};
 
@@ -292,15 +259,13 @@ void pcie_setup_hoses(int busno)
 
        for (i = 0; i < 2; i++) {
 
-               if (is_end_point(i)) {
-                       printf("PCIE%d: will be configured as endpoint\n", i);
+               if (is_end_point(i))
                        ret = ppc4xx_init_pcie_endport(i);
-               } else {
-                       printf("PCIE%d: will be configured as root-complex\n", i);
+               else
                        ret = ppc4xx_init_pcie_rootport(i);
-               }
                if (ret) {
-                       printf("PCIE%d: initialization failed\n", i);
+                       printf("PCIE%d: initialization as %s failed\n", i,
+                              is_end_point(i) ? "endpoint" : "root-complex");
                        continue;
                }
 

diff --git a/include/configs/makalu.h b/include/configs/makalu.h
index 30707799f5c602be6d373bbc65f8ca98e08c7f8c..aa421c1392a82c751e08ced1d8120dfc5559e1a0 100644 (file)
--- a/include/configs/makalu.h
+++ b/include/configs/makalu.h
@@ -44,11 +44,11 @@
  * actual resources get mapped (not physical addresses)
  *----------------------------------------------------------------------*/
 #define CFG_SDRAM_BASE         0x00000000
-#define CFG_FLASH_BASE         0xFE000000
+#define CFG_FLASH_BASE         0xFC000000
 #define CFG_FPGA_BASE          0xF0000000
 #define CFG_PERIPHERAL_BASE    0xEF600000      /* internal peripherals*/
 #define CFG_MONITOR_LEN                (384 * 1024)    /* Reserve 384 kB for Monitor   */
-#define CFG_MALLOC_LEN         (128 * 1024)    /* Reserve 128 kB for malloc()  */
+#define CFG_MALLOC_LEN         (512 * 1024)    /* Reserve 512 kB for malloc()  */
 #define CFG_MONITOR_BASE       (TEXT_BASE)
 
 /*-----------------------------------------------------------------------
@@ -113,7 +113,7 @@
 /*-----------------------------------------------------------------------
  * DDR SDRAM
  *----------------------------------------------------------------------*/
-#define CFG_MBYTES_SDRAM        128
+#define CFG_MBYTES_SDRAM       256
 
 /*-----------------------------------------------------------------------
  * I2C
@@ -150,7 +150,7 @@
 
 #define CONFIG_NET_MULTI       1
 #define CONFIG_HAS_ETH1                1       /* add support for "eth1addr"   */
-#define CONFIG_PHY1_ADDR       2
+#define CONFIG_PHY1_ADDR       0
 
 #define CFG_RX_ETH_BUFFER      32      /* Number of ethernet rx buffers & descriptors */
 
@@ -187,8 +187,8 @@
        "bootfile=makalu/uImage\0"                                      \
        "fdt_file=makalu/makalu.dtb\0"                                  \
        "fdt_addr=400000\0"                                             \
-       "kernel_addr=fe000000\0"                                        \
-       "ramdisk_addr=fe200000\0"                                       \
+       "kernel_addr=fc000000\0"                                        \
+       "ramdisk_addr=fc200000\0"                                       \
        "initrd_high=30000000\0"                                        \
        "load=tftp 200000 makalu/u-boot.bin\0"                          \
        "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;"   \
@@ -282,6 +282,7 @@
 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 #define CONFIG_ZERO_BOOTDELAY_CHECK    /* check for keypress on bootdelay==0 */
 #define CONFIG_VERSION_VARIABLE 1      /* include version env variable */
+#define CFG_CONSOLE_INFO_QUIET 1       /* don't print console @ startup*/
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -323,7 +324,7 @@
  *----------------------------------------------------------------------*/
 /* Memory Bank 0 (NOR-FLASH) initialization                                    */
 #define CFG_EBC_PB0AP          0x04011000
-#define CFG_EBC_PB0CR           0xFE0BA000  /* BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit*/
+#define CFG_EBC_PB0CR          (CFG_FLASH_BASE | 0xda000)
 
 /* Memory Bank 2 (CPLD) initialization                                         */
 #define CFG_EBC_PB2AP           0x9400C800
@@ -334,28 +335,47 @@
 /*-----------------------------------------------------------------------
  * GPIO Setup
  *----------------------------------------------------------------------*/
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EX specific)
- *
- * GPIO0[0-3]      - EBC data 0-3      inputs/outputs
- * GPIO0[4-7]      - USB data 4-7      inputs/outputs
- * GPIO0[8-11]     - NFCE# 1-3 inputs/outputs, GPIO11: IRQ6 inputs
- * GPIO0[12-15]    - USB data 0-3      inputs/outputs
- * GPIO0[16-21]    - UART0 control signal inputs/outputs
- *
- * GPIO0[22-25,27] - EBC control signal inputs/outputs
- * GPIO0[26]      - Instruction trace outputs
- * GPIO0[28]      - Float, N/C
- * GPIO0[29-31]    - DMA control signal inputs/outputs
- */
-#define CFG_GPIO0_OSRL         0x00AA54AA
-#define CFG_GPIO0_OSRH         0x55500000
-#define CFG_GPIO0_TSRL         0x00AA54AA
-#define CFG_GPIO0_TSRH         0x55500000
-#define CFG_GPIO0_ISR1L                0x00005400
-#define CFG_GPIO0_ISR1H                0x55500000
-#define CFG_GPIO0_ISR2L                0x00550055
-#define CFG_GPIO0_ISR2H                0x00000000
+#define CFG_4xx_GPIO_TABLE { /*          Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
+{                                                                                      \
+/* GPIO Core 0 */                                                                      \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO0        EBC_DATA_PAR(0)                 */      \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO1        EBC_DATA_PAR(1)                 */      \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO2        EBC_DATA_PAR(2)                 */      \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO3        EBC_DATA_PAR(3)                 */      \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO4        EBC_DATA(20)    USB2_DATA(4)    */      \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO5        EBC_DATA(21)    USB2_DATA(5)    */      \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO6        EBC_DATA(22)    USB2_DATA(6)    */      \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO7        EBC_DATA(23)    USB2_DATA(7)    */      \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8        EBC_CS(1)       NFCE(1)         IRQ(7) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9        EBC_CS(2)       NFCE(2)         IRQ(8) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS(3)     NFCE(3)         IRQ(9) */ \
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 IRQ(6)                                */      \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16)  USB2_DATA(0)    */      \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17)  USB2_DATA(1)    */      \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO14 EBC_DATA(18)  USB2_DATA(2)    */      \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO15 EBC_DATA(19)  USB2_DATA(3)    */      \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD     UART1_CTS       */      \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR     UART1_RTS       */      \
+{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS                     */      \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS                     */      \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO20 UART0_DTR     UART1_TX        */      \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO21 UART0_RI      UART1_RX        */      \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ  DMA_ACK2        */      \
+{GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK  DMA_REQ2        */      \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ   DMA_EOT2        IRQ(4) */ \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK   DMA_ACK3        IRQ(3) */ \
+{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5)   DMA_EOT0        TS(3) */ \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ   DMA_EOT3        IRQ(5) */ \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO28                               */      \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO29 IRQ(2)                DMA_EOT1        */      \
+{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 IRQ(1)                DMA_REQ1        */      \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO31 IRQ(0)                DMA_ACK1        */      \
+}                                                                                              \
+}
+
+#define CFG_GPIO_PCIE_RST      23
+#define CFG_GPIO_PCIE_CLKREQ   27
+#define CFG_GPIO_PCIE_WAKE     28
 
 /*
  * Internal Definitions