global: Move remaining CONFIG_SYS_PCI* to CFG_SYS_PCI*

The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_PCI and
CONFIG_SYS_PCIE namespace do not easily transition to Kconfig. In many
cases they likely should come from the device tree instead. Move these
out of CONFIG namespace and in to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index d530e0655bc25629d145e84bddd32516a666e912..d09c21d5d9b2d6d0b01e307a39e6a23067b61630 100644 (file)
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -168,18 +168,18 @@ static void mmu_setup(void)
        /* Level 1 has 512 entries */
        for (i = 0; i < 512; i++) {
                /* Mapping for PCIe 1 */
-               if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR &&
-                   va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR +
-                                CONFIG_SYS_PCIE_MMAP_SIZE))
+               if (va_start >= CFG_SYS_PCIE1_VIRT_ADDR &&
+                   va_start < (CFG_SYS_PCIE1_VIRT_ADDR +
+                                CFG_SYS_PCIE_MMAP_SIZE))
                        set_pgsection(level1_table, i,
-                                     CONFIG_SYS_PCIE1_PHYS_BASE + va_start,
+                                     CFG_SYS_PCIE1_PHYS_BASE + va_start,
                                      MT_DEVICE_MEM);
                /* Mapping for PCIe 2 */
-               else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR &&
-                        va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR +
-                                    CONFIG_SYS_PCIE_MMAP_SIZE))
+               else if (va_start >= CFG_SYS_PCIE2_VIRT_ADDR &&
+                        va_start < (CFG_SYS_PCIE2_VIRT_ADDR +
+                                    CFG_SYS_PCIE_MMAP_SIZE))
                        set_pgsection(level1_table, i,
-                                     CONFIG_SYS_PCIE2_PHYS_BASE + va_start,
+                                     CFG_SYS_PCIE2_PHYS_BASE + va_start,
                                      MT_DEVICE_MEM);
                else
                        set_pgsection(level1_table, i,

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index c11341a1d380eb85545946d986f86b8e015f7dc6..ef71e2cf2bca5b6d8dd157ec8a248156eb0c79ce 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -257,26 +257,26 @@ static struct mm_region final_map[] = {
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
        },
-       { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
-         CONFIG_SYS_PCIE1_PHYS_SIZE,
+       { CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR,
+         CFG_SYS_PCIE1_PHYS_SIZE,
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
        },
-       { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
-         CONFIG_SYS_PCIE2_PHYS_SIZE,
+       { CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR,
+         CFG_SYS_PCIE2_PHYS_SIZE,
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
        },
-#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
-       { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
-         CONFIG_SYS_PCIE3_PHYS_SIZE,
+#ifdef CFG_SYS_PCIE3_PHYS_ADDR
+       { CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR,
+         CFG_SYS_PCIE3_PHYS_SIZE,
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
        },
 #endif
-#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
-       { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
-         CONFIG_SYS_PCIE4_PHYS_SIZE,
+#ifdef CFG_SYS_PCIE4_PHYS_ADDR
+       { CFG_SYS_PCIE4_PHYS_ADDR, CFG_SYS_PCIE4_PHYS_ADDR,
+         CFG_SYS_PCIE4_PHYS_SIZE,
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
        },
@@ -368,19 +368,19 @@ static struct mm_region final_map[] = {
          PTE_BLOCK_MEMTYPE(MT_NORMAL) |
          PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
        },
-       { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
-         CONFIG_SYS_PCIE1_PHYS_SIZE,
+       { CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR,
+         CFG_SYS_PCIE1_PHYS_SIZE,
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
        },
-       { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
-         CONFIG_SYS_PCIE2_PHYS_SIZE,
+       { CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR,
+         CFG_SYS_PCIE2_PHYS_SIZE,
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
        },
-#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
-       { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
-         CONFIG_SYS_PCIE3_PHYS_SIZE,
+#ifdef CFG_SYS_PCIE3_PHYS_ADDR
+       { CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR,
+         CFG_SYS_PCIE3_PHYS_SIZE,
          PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
        },
@@ -477,25 +477,25 @@ static void fix_pcie_mmu_map(void)
            (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
                for (i = 0; i < ARRAY_SIZE(final_map); i++) {
                        switch (final_map[i].phys) {
-                       case CONFIG_SYS_PCIE1_PHYS_ADDR:
+                       case CFG_SYS_PCIE1_PHYS_ADDR:
                                final_map[i].phys = 0x2000000000ULL;
                                final_map[i].virt = 0x2000000000ULL;
                                final_map[i].size = 0x800000000ULL;
                                break;
-                       case CONFIG_SYS_PCIE2_PHYS_ADDR:
+                       case CFG_SYS_PCIE2_PHYS_ADDR:
                                final_map[i].phys = 0x2800000000ULL;
                                final_map[i].virt = 0x2800000000ULL;
                                final_map[i].size = 0x800000000ULL;
                                break;
-#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
-                       case CONFIG_SYS_PCIE3_PHYS_ADDR:
+#ifdef CFG_SYS_PCIE3_PHYS_ADDR
+                       case CFG_SYS_PCIE3_PHYS_ADDR:
                                final_map[i].phys = 0x3000000000ULL;
                                final_map[i].virt = 0x3000000000ULL;
                                final_map[i].size = 0x800000000ULL;
                                break;
 #endif
-#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
-                       case CONFIG_SYS_PCIE4_PHYS_ADDR:
+#ifdef CFG_SYS_PCIE4_PHYS_ADDR
+                       case CFG_SYS_PCIE4_PHYS_ADDR:
                                final_map[i].phys = 0x3800000000ULL;
                                final_map[i].virt = 0x3800000000ULL;
                                final_map[i].size = 0x800000000ULL;

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 4db479140ea2e3af78e95f19807c9f6923a1ffad..20f96713871a0b439f6d402a68a8460cc7a42b0c 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -35,17 +35,17 @@
 #define CONFIG_SYS_FSL_QBMAN_SIZE      0x8000000
 #define CONFIG_SYS_FSL_QBMAN_SIZE_1    0x4000000
 #ifdef CONFIG_ARCH_LS2080A
-#define CONFIG_SYS_PCIE1_PHYS_SIZE     0x200000000
-#define CONFIG_SYS_PCIE2_PHYS_SIZE     0x200000000
-#define CONFIG_SYS_PCIE3_PHYS_SIZE     0x200000000
-#define CONFIG_SYS_PCIE4_PHYS_SIZE     0x200000000
+#define CFG_SYS_PCIE1_PHYS_SIZE        0x200000000
+#define CFG_SYS_PCIE2_PHYS_SIZE        0x200000000
+#define CFG_SYS_PCIE3_PHYS_SIZE        0x200000000
+#define CFG_SYS_PCIE4_PHYS_SIZE        0x200000000
 #else
-#define CONFIG_SYS_PCIE1_PHYS_SIZE     0x800000000
-#define CONFIG_SYS_PCIE2_PHYS_SIZE     0x800000000
-#ifndef CONFIG_SYS_PCIE3_PHYS_SIZE
-#define CONFIG_SYS_PCIE3_PHYS_SIZE     0x800000000
+#define CFG_SYS_PCIE1_PHYS_SIZE        0x800000000
+#define CFG_SYS_PCIE2_PHYS_SIZE        0x800000000
+#ifndef CFG_SYS_PCIE3_PHYS_SIZE
+#define CFG_SYS_PCIE3_PHYS_SIZE        0x800000000
 #endif
-#define CONFIG_SYS_PCIE4_PHYS_SIZE     0x800000000
+#define CFG_SYS_PCIE4_PHYS_SIZE        0x800000000
 #define SYS_PCIE5_PHYS_SIZE            0x800000000
 #define SYS_PCIE6_PHYS_SIZE            0x800000000
 #endif
@@ -83,9 +83,9 @@
 #define CONFIG_SYS_FSL_QBMAN_SIZE      0x10000000
 #define CONFIG_SYS_FSL_DRAM_BASE2      0x880000000
 #define CONFIG_SYS_FSL_DRAM_SIZE2      0x780000000     /* 30GB */
-#define CONFIG_SYS_PCIE1_PHYS_SIZE     0x800000000
-#define CONFIG_SYS_PCIE2_PHYS_SIZE     0x800000000
-#define CONFIG_SYS_PCIE3_PHYS_SIZE     0x800000000
+#define CFG_SYS_PCIE1_PHYS_SIZE        0x800000000
+#define CFG_SYS_PCIE2_PHYS_SIZE        0x800000000
+#define CFG_SYS_PCIE3_PHYS_SIZE        0x800000000
 #define CONFIG_SYS_FSL_DRAM_BASE3      0x8800000000
 #define CONFIG_SYS_FSL_DRAM_SIZE3      0x7800000000    /* 480GB */
 #endif

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 85ac5eb28138356c4d75916027b23b4852557dce..64dc7c88b7f8a175506834dab22ffeffd84072d0 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -33,8 +33,8 @@
 #define CONFIG_SYS_XHCI_USB1_ADDR              (CONFIG_SYS_IMMR + 0x01f00000)
 #define CONFIG_SYS_XHCI_USB2_ADDR              (CONFIG_SYS_IMMR + 0x02000000)
 #define CONFIG_SYS_XHCI_USB3_ADDR              (CONFIG_SYS_IMMR + 0x02100000)
-#define CONFIG_SYS_PCIE1_ADDR                  (CONFIG_SYS_IMMR + 0x2400000)
-#define CONFIG_SYS_PCIE2_ADDR                  (CONFIG_SYS_IMMR + 0x2500000)
+#define CFG_SYS_PCIE1_ADDR                     (CONFIG_SYS_IMMR + 0x2400000)
+#define CFG_SYS_PCIE2_ADDR                     (CONFIG_SYS_IMMR + 0x2500000)
 #define CONFIG_SYS_SEC_MON_ADDR                        (CONFIG_SYS_IMMR + 0xe90000)
 #define CONFIG_SYS_SFP_ADDR                    (CONFIG_SYS_IMMR + 0xe80200)
 
@@ -90,9 +90,9 @@
 #define QDMA_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x07380000)
 #define QMAN_CQSIDR_REG                                0x20a80
 
-#define CONFIG_SYS_PCIE1_PHYS_ADDR             0x4000000000ULL
-#define CONFIG_SYS_PCIE2_PHYS_ADDR             0x4800000000ULL
-#define CONFIG_SYS_PCIE3_PHYS_ADDR             0x5000000000ULL
+#define CFG_SYS_PCIE1_PHYS_ADDR                0x4000000000ULL
+#define CFG_SYS_PCIE2_PHYS_ADDR                0x4800000000ULL
+#define CFG_SYS_PCIE3_PHYS_ADDR                0x5000000000ULL
 /* LUT registers */
 #ifdef CONFIG_ARCH_LS1012A
 #define PCIE_LUT_BASE                          0xC0000

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 59488a04e409aeb45d2176ed249c5186da84c5fb..cd112402e0c829b89c11649554a172db5529690a 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -192,35 +192,35 @@
 
 
 /* PCIe */
-#define CONFIG_SYS_PCIE1_ADDR                  (CONFIG_SYS_IMMR + 0x2400000)
-#define CONFIG_SYS_PCIE2_ADDR                  (CONFIG_SYS_IMMR + 0x2500000)
+#define CFG_SYS_PCIE1_ADDR                     (CONFIG_SYS_IMMR + 0x2400000)
+#define CFG_SYS_PCIE2_ADDR                     (CONFIG_SYS_IMMR + 0x2500000)
 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
 #define SYS_PCIE5_ADDR                         (CONFIG_SYS_IMMR + 0x2800000)
 #define SYS_PCIE6_ADDR                         (CONFIG_SYS_IMMR + 0x2900000)
 #endif
 
 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
-#define CONFIG_SYS_PCIE1_PHYS_ADDR             0x8000000000ULL
-#define CONFIG_SYS_PCIE2_PHYS_ADDR             0x8800000000ULL
-#define CONFIG_SYS_PCIE3_PHYS_ADDR             0x9000000000ULL
-#define CONFIG_SYS_PCIE4_PHYS_ADDR             0x9800000000ULL
+#define CFG_SYS_PCIE1_PHYS_ADDR                0x8000000000ULL
+#define CFG_SYS_PCIE2_PHYS_ADDR                0x8800000000ULL
+#define CFG_SYS_PCIE3_PHYS_ADDR                0x9000000000ULL
+#define CFG_SYS_PCIE4_PHYS_ADDR                0x9800000000ULL
 #define SYS_PCIE5_PHYS_ADDR                    0xa000000000ULL
 #define SYS_PCIE6_PHYS_ADDR                    0xa800000000ULL
 #elif CONFIG_ARCH_LS1088A
-#define CONFIG_SYS_PCIE1_PHYS_ADDR             0x2000000000ULL
-#define CONFIG_SYS_PCIE2_PHYS_ADDR             0x2800000000ULL
-#define CONFIG_SYS_PCIE3_PHYS_ADDR             0x3000000000ULL
+#define CFG_SYS_PCIE1_PHYS_ADDR                0x2000000000ULL
+#define CFG_SYS_PCIE2_PHYS_ADDR                0x2800000000ULL
+#define CFG_SYS_PCIE3_PHYS_ADDR                0x3000000000ULL
 #elif CONFIG_ARCH_LS1028A
-#define CONFIG_SYS_PCIE1_PHYS_ADDR             0x8000000000ULL
-#define CONFIG_SYS_PCIE2_PHYS_ADDR             0x8800000000ULL
-#define CONFIG_SYS_PCIE3_PHYS_ADDR             0x01f0000000ULL
+#define CFG_SYS_PCIE1_PHYS_ADDR                0x8000000000ULL
+#define CFG_SYS_PCIE2_PHYS_ADDR                0x8800000000ULL
+#define CFG_SYS_PCIE3_PHYS_ADDR                0x01f0000000ULL
 /* this is used by integrated PCI on LS1028, includes ECAM and register space */
-#define CONFIG_SYS_PCIE3_PHYS_SIZE             0x0010000000ULL
+#define CFG_SYS_PCIE3_PHYS_SIZE                0x0010000000ULL
 #else
-#define CONFIG_SYS_PCIE1_PHYS_ADDR             0x1000000000ULL
-#define CONFIG_SYS_PCIE2_PHYS_ADDR             0x1200000000ULL
-#define CONFIG_SYS_PCIE3_PHYS_ADDR             0x1400000000ULL
-#define CONFIG_SYS_PCIE4_PHYS_ADDR             0x1600000000ULL
+#define CFG_SYS_PCIE1_PHYS_ADDR                0x1000000000ULL
+#define CFG_SYS_PCIE2_PHYS_ADDR                0x1200000000ULL
+#define CFG_SYS_PCIE3_PHYS_ADDR                0x1400000000ULL
+#define CFG_SYS_PCIE4_PHYS_ADDR                0x1600000000ULL
 #endif
 
 /* Device Configuration */

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 033341dbfb631b3c2531ddf9ee4812f9ebd19891..62026bda9e2b71eb570f54e7bec8bc4b401077c4 100644 (file)
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -55,22 +55,22 @@
 
 #define LPUART_BASE                            (CONFIG_SYS_IMMR + 0x01950000)
 
-#define CONFIG_SYS_PCIE1_ADDR                  (CONFIG_SYS_IMMR + 0x2400000)
-#define CONFIG_SYS_PCIE2_ADDR                  (CONFIG_SYS_IMMR + 0x2500000)
-
-#define CONFIG_SYS_PCIE1_PHYS_BASE             0x4000000000ULL
-#define CONFIG_SYS_PCIE2_PHYS_BASE             0x4800000000ULL
-#define CONFIG_SYS_PCIE1_VIRT_ADDR             0x24000000UL
-#define CONFIG_SYS_PCIE2_VIRT_ADDR             0x34000000UL
-#define CONFIG_SYS_PCIE_MMAP_SIZE              (192 * 1024 * 1024) /* 192M */
+#define CFG_SYS_PCIE1_ADDR                     (CONFIG_SYS_IMMR + 0x2400000)
+#define CFG_SYS_PCIE2_ADDR                     (CONFIG_SYS_IMMR + 0x2500000)
+
+#define CFG_SYS_PCIE1_PHYS_BASE                0x4000000000ULL
+#define CFG_SYS_PCIE2_PHYS_BASE                0x4800000000ULL
+#define CFG_SYS_PCIE1_VIRT_ADDR                0x24000000UL
+#define CFG_SYS_PCIE2_VIRT_ADDR                0x34000000UL
+#define CFG_SYS_PCIE_MMAP_SIZE         (192 * 1024 * 1024) /* 192M */
 /*
  * TLB will map VIRT_ADDR to (PHYS_BASE + VIRT_ADDR)
  * So 40bit PCIe PHY addr can directly be converted to a 32bit virtual addr.
  */
-#define CONFIG_SYS_PCIE1_PHYS_ADDR             (CONFIG_SYS_PCIE1_PHYS_BASE + \
-                                                CONFIG_SYS_PCIE1_VIRT_ADDR)
-#define CONFIG_SYS_PCIE2_PHYS_ADDR             (CONFIG_SYS_PCIE2_PHYS_BASE + \
-                                                CONFIG_SYS_PCIE2_VIRT_ADDR)
+#define CFG_SYS_PCIE1_PHYS_ADDR                (CFG_SYS_PCIE1_PHYS_BASE + \
+                                                CFG_SYS_PCIE1_VIRT_ADDR)
+#define CFG_SYS_PCIE2_PHYS_ADDR                (CFG_SYS_PCIE2_PHYS_BASE + \
+                                                CFG_SYS_PCIE2_VIRT_ADDR)
 
 /* SATA */
 #define AHCI_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x02200000)

diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h
index ead62cd03871ff701d2e596fe1961ea7593f5e60..f2eb6fcb463b04bcdb1787ce81d81c950ed0ed47 100644 (file)
--- a/arch/m68k/include/asm/immap.h
+++ b/arch/m68k/include/asm/immap.h
@@ -337,10 +337,10 @@
 #define CONFIG_SYS_NUM_IRQS            (128)
 
 #ifdef CONFIG_PCI
-#define CONFIG_SYS_PCI_BAR0            (0x40000000)
-#define CONFIG_SYS_PCI_BAR1            (CONFIG_SYS_SDRAM_BASE)
-#define CONFIG_SYS_PCI_TBATR0          (CONFIG_SYS_MBAR)
-#define CONFIG_SYS_PCI_TBATR1          (CONFIG_SYS_SDRAM_BASE)
+#define CFG_SYS_PCI_BAR0               (0x40000000)
+#define CFG_SYS_PCI_BAR1               (CONFIG_SYS_SDRAM_BASE)
+#define CFG_SYS_PCI_TBATR0             (CONFIG_SYS_MBAR)
+#define CFG_SYS_PCI_TBATR1             (CONFIG_SYS_SDRAM_BASE)
 #endif
 #endif                         /* CONFIG_M547x */
 

diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c
index d2b6b05bdaf9c1ec5d457f56be06da5f7ca3c069..47ca74c5c35686101bf6ec262b5f0a3960a4d746 100644 (file)
--- a/arch/powerpc/cpu/mpc83xx/pcie.c
+++ b/arch/powerpc/cpu/mpc83xx/pcie.c
@@ -24,13 +24,13 @@ static struct {
        u32 size;
 } mpc83xx_pcie_cfg_space[] = {
        {
-               .base = CONFIG_SYS_PCIE1_CFG_BASE,
-               .size = CONFIG_SYS_PCIE1_CFG_SIZE,
+               .base = CFG_SYS_PCIE1_CFG_BASE,
+               .size = CFG_SYS_PCIE1_CFG_SIZE,
        },
-#if defined(CONFIG_SYS_PCIE2_CFG_BASE) && defined(CONFIG_SYS_PCIE2_CFG_SIZE)
+#if defined(CFG_SYS_PCIE2_CFG_BASE) && defined(CFG_SYS_PCIE2_CFG_SIZE)
        {
-               .base = CONFIG_SYS_PCIE2_CFG_BASE,
-               .size = CONFIG_SYS_PCIE2_CFG_SIZE,
+               .base = CFG_SYS_PCIE2_CFG_BASE,
+               .size = CFG_SYS_PCIE2_CFG_SIZE,
        },
 #endif
 };

diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index abc14fae4ec087ff9dc602f71e7e263a7683e473..d5df02d39d8225229c1da3d2a950af3d60c21d70 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -387,7 +387,7 @@ void fdt_fixup_liodn(void *blob)
        fdt_fixup_liodn_tbl(blob, rman_liodn_tbl, rman_liodn_tbl_sz);
 #endif
 
-       ccsr_pcix_t *pcix = (ccsr_pcix_t *)CONFIG_SYS_PCIE1_ADDR;
+       ccsr_pcix_t *pcix = (ccsr_pcix_t *)CFG_SYS_PCIE1_ADDR;
        int pci_ver = pcix->ipver1 & 0xffff, liodn_base = 0;
 
        if (pci_ver >= 0x0204) {

diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h
index 06f9bfb8ac73213a0544ce3431a92fbe875a0ee3..809ab1d4187ed7d7252ed4c7870b5488593b0211 100644 (file)
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -193,35 +193,35 @@ int fsl_pcie_init_board(int busno);
 
 #define SET_STD_PCI_INFO(x, num) \
 {                      \
-       x.regs = CONFIG_SYS_PCI##num##_ADDR;    \
-       x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \
-       x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \
-       x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \
-       x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \
-       x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \
-       x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \
+       x.regs = CFG_SYS_PCI##num##_ADDR;       \
+       x.mem_bus = CFG_SYS_PCI##num##_MEM_BUS; \
+       x.mem_phys = CFG_SYS_PCI##num##_MEM_PHYS; \
+       x.mem_size = CFG_SYS_PCI##num##_MEM_SIZE; \
+       x.io_bus = CFG_SYS_PCI##num##_IO_BUS; \
+       x.io_phys = CFG_SYS_PCI##num##_IO_PHYS; \
+       x.io_size = CFG_SYS_PCI##num##_IO_SIZE; \
        x.law = LAW_TRGT_IF_PCI_##num; \
        x.pci_num = num; \
 }
 
 #define SET_STD_PCIE_INFO(x, num) \
 {                      \
-       x.regs = CONFIG_SYS_PCIE##num##_ADDR;   \
-       x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \
-       x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \
-       x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \
-       x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \
-       x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \
-       x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \
+       x.regs = CFG_SYS_PCIE##num##_ADDR;      \
+       x.mem_bus = CFG_SYS_PCIE##num##_MEM_BUS; \
+       x.mem_phys = CFG_SYS_PCIE##num##_MEM_PHYS; \
+       x.mem_size = CFG_SYS_PCIE##num##_MEM_SIZE; \
+       x.io_bus = CFG_SYS_PCIE##num##_IO_BUS; \
+       x.io_phys = CFG_SYS_PCIE##num##_IO_PHYS; \
+       x.io_size = CFG_SYS_PCIE##num##_IO_SIZE; \
        x.law = LAW_TRGT_IF_PCIE_##num; \
        x.pci_num = num; \
 }
 
 #define __FT_FSL_PCI_SETUP(blob, compat, num) \
-       ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCI##num##_ADDR)
+       ft_fsl_pci_setup(blob, compat, CFG_SYS_PCI##num##_ADDR)
 
 #define __FT_FSL_PCIE_SETUP(blob, compat, num) \
-       ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCIE##num##_ADDR)
+       ft_fsl_pci_setup(blob, compat, CFG_SYS_PCIE##num##_ADDR)
 
 #define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1)
 #define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2)

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 78c0d05496551a32df55ed1efa305a38c318e594..9ae698743eee3e23872f4c7118b1193957aea339 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2662,9 +2662,9 @@ struct ccsr_pman {
 #define CONFIG_SYS_PAMU_ADDR \
        (CONFIG_SYS_IMMR + CFG_SYS_FSL_PAMU_OFFSET)
 
-#define CONFIG_SYS_PCIE1_ADDR \
+#define CFG_SYS_PCIE1_ADDR \
        (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE1_OFFSET)
-#define CONFIG_SYS_PCIE2_ADDR \
+#define CFG_SYS_PCIE2_ADDR \
        (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE2_OFFSET)
 
 #define CONFIG_SYS_SFP_ADDR  \

diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c
index ef46353a3670ada2ddd16f7dc288140935548066..4cdef89bf0eedd8ea6b664bac564813c7ed31142 100644 (file)
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -91,23 +91,23 @@ struct fsl_e_tlb_entry tlb_table[] = {
                      0, 2, BOOKE_PAGESZ_256M, 1),
 
        /* *I*G* - PCI */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
                      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 3, BOOKE_PAGESZ_1G, 1),
 
        /* *I*G* - PCI */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
-                     CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x40000000,
+                     CFG_SYS_PCIE1_MEM_PHYS + 0x40000000,
                      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 4, BOOKE_PAGESZ_256M, 1),
 
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
-                     CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x50000000,
+                     CFG_SYS_PCIE1_MEM_PHYS + 0x50000000,
                      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 5, BOOKE_PAGESZ_256M, 1),
 
        /* *I*G* - PCI I/O */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
                      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 6, BOOKE_PAGESZ_256K, 1),
 

diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c
index 8d1e5fee9365c073b08f66112106ab98d40ed6b9..9c8e9486008974a7941fe110be260859d898cec5 100644 (file)
--- a/board/freescale/mpc8548cds/tlb.c
+++ b/board/freescale/mpc8548cds/tlb.c
@@ -62,7 +62,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
         * Entry 4:
         * PCI and PCIe MEM     1G      Non-cacheable, guarded
         */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCI1_MEM_VIRT, CFG_SYS_PCI1_MEM_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 4, BOOKE_PAGESZ_1G, 1),
 
@@ -70,7 +70,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
         * Entry 5:
         * PCI1 IO      1M      Non-cacheable, guarded
         */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCI1_IO_VIRT, CFG_SYS_PCI1_IO_PHYS,
                      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 5, BOOKE_PAGESZ_1M, 1),
 
@@ -78,7 +78,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
         * Entry 6:
         * PCIe IO      1M      Non-cacheable, guarded
         */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
                      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 6, BOOKE_PAGESZ_1M, 1),
 };

diff --git a/board/freescale/p1010rdb/tlb.c b/board/freescale/p1010rdb/tlb.c
index aa7517a74d819c222084e9a8ff2696cf24e30652..5e1fa70bca559a092db68c172bbd828ab8042a38 100644 (file)
--- a/board/freescale/p1010rdb/tlb.c
+++ b/board/freescale/p1010rdb/tlb.c
@@ -52,12 +52,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #ifdef CONFIG_PCI
        /* *I*G* - PCI */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
                        MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 4, BOOKE_PAGESZ_1G, 1),
 
        /* *I*G* - PCI I/O */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
                        MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 5, BOOKE_PAGESZ_256K, 1),
 #endif

diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 85d41327aa24e4cb31445e509e50d7af80e4dd36..4cc5e01f5789aea0f234cf7c9dac66a65450e4bf 100644 (file)
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -45,12 +45,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #ifdef CONFIG_PCI
        /* *I*G* - PCI memory 1.5G */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 3, BOOKE_PAGESZ_1G, 1),
 
        /* *I*G* - PCI I/O effective: 192K  */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 4, BOOKE_PAGESZ_256K, 1),
 #endif

diff --git a/board/freescale/t102xrdb/tlb.c b/board/freescale/t102xrdb/tlb.c
index 8fdff7576fe55b70559140169df4eae9f1e9a39d..74744c8ab0ad284670c15a8d72c2ca1644b8f66b 100644 (file)
--- a/board/freescale/t102xrdb/tlb.c
+++ b/board/freescale/t102xrdb/tlb.c
@@ -54,12 +54,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #ifndef CONFIG_SPL_BUILD
        /* *I*G* - PCI */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 3, BOOKE_PAGESZ_1G, 1),
 
        /* *I*G* - PCI I/O */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 4, BOOKE_PAGESZ_256K, 1),
 

diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c
index 8a3d67449c27c7058aafccabd4ef5645c02fe80d..905e4771c91e1fc26a1e14f17a40559795c0623a 100644 (file)
--- a/board/freescale/t104xrdb/tlb.c
+++ b/board/freescale/t104xrdb/tlb.c
@@ -67,12 +67,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #ifndef CONFIG_SPL_BUILD
        /* *I*G* - PCI */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 3, BOOKE_PAGESZ_1G, 1),
 
        /* *I*G* - PCI I/O */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 4, BOOKE_PAGESZ_256K, 1),
 

diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c
index f27faf5d243758482d3b4df964d7a9a7dd832a0a..9160674b94fd0e6ab75b7bcca6ebde98ad801ff7 100644 (file)
--- a/board/freescale/t208xqds/tlb.c
+++ b/board/freescale/t208xqds/tlb.c
@@ -66,28 +66,28 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #ifndef CONFIG_SPL_BUILD
        /* *I*G* - PCIe 1, 0x80000000 */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 3, BOOKE_PAGESZ_512M, 1),
 
        /* *I*G* - PCIe 2, 0xa0000000 */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE2_MEM_VIRT, CFG_SYS_PCIE2_MEM_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 4, BOOKE_PAGESZ_256M, 1),
 
        /* *I*G* - PCIe 3, 0xb0000000 */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE3_MEM_VIRT, CFG_SYS_PCIE3_MEM_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 5, BOOKE_PAGESZ_256M, 1),
 
 
        /* *I*G* - PCIe 4, 0xc0000000 */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE4_MEM_VIRT, CFG_SYS_PCIE4_MEM_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 6, BOOKE_PAGESZ_256M, 1),
 
        /* *I*G* - PCI I/O */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 7, BOOKE_PAGESZ_256K, 1),
 

diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c
index da03aadb173348c082e6fff9a7909a848fc030ca..69e58e7e9732ccead9f1edda97569025c95daa82 100644 (file)
--- a/board/freescale/t208xrdb/tlb.c
+++ b/board/freescale/t208xrdb/tlb.c
@@ -66,28 +66,28 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #ifndef CONFIG_SPL_BUILD
        /* *I*G* - PCIe 1, 0x80000000 */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 3, BOOKE_PAGESZ_512M, 1),
 
        /* *I*G* - PCIe 2, 0xa0000000 */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE2_MEM_VIRT, CFG_SYS_PCIE2_MEM_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 4, BOOKE_PAGESZ_256M, 1),
 
        /* *I*G* - PCIe 3, 0xb0000000 */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE3_MEM_VIRT, CFG_SYS_PCIE3_MEM_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 5, BOOKE_PAGESZ_256M, 1),
 
 
        /* *I*G* - PCIe 4, 0xc0000000 */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE4_MEM_VIRT, CFG_SYS_PCIE4_MEM_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 6, BOOKE_PAGESZ_256M, 1),
 
        /* *I*G* - PCI I/O */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 7, BOOKE_PAGESZ_256K, 1),
 

diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c
index 059449af1edf3f5650e30e9cef816a9a1ce701ce..c57af3046f91b704951db6f1de737615dd25af14 100644 (file)
--- a/board/freescale/t4rdb/tlb.c
+++ b/board/freescale/t4rdb/tlb.c
@@ -52,23 +52,23 @@ struct fsl_e_tlb_entry tlb_table[] = {
 
 #ifndef CONFIG_SPL_BUILD
        /* *I*G* - PCI */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 3, BOOKE_PAGESZ_1G, 1),
 
        /* *I*G* - PCI */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
-                     CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x40000000,
+                     CFG_SYS_PCIE1_MEM_PHYS + 0x40000000,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 4, BOOKE_PAGESZ_256M, 1),
 
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
-                     CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT + 0x50000000,
+                     CFG_SYS_PCIE1_MEM_PHYS + 0x50000000,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 5, BOOKE_PAGESZ_256M, 1),
 
        /* *I*G* - PCI I/O */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 6, BOOKE_PAGESZ_256K, 1),
 

diff --git a/board/keymile/kmcent2/tlb.c b/board/keymile/kmcent2/tlb.c
index 095fc7e96146f00f74be3aeede28ec52c7321e05..0f6dc6063ab1f600d8a1b17cc8a936bd92628c97 100644 (file)
--- a/board/keymile/kmcent2/tlb.c
+++ b/board/keymile/kmcent2/tlb.c
@@ -46,12 +46,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
                      0, 2, BOOKE_PAGESZ_128M, 1),
 
        /* *I*G* - PCI1 */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
                      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
                      0, 3, BOOKE_PAGESZ_1G, 1),
 
        /* *I*G* - PCI1 I/O */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
                      MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
                      0, 4, BOOKE_PAGESZ_256K, 1),
 

diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c
index de80c3c0e5734625cbcd22726ab9d0017b42bb06..1ab403d145e610f916aa349efbce31124ef27d94 100644 (file)
--- a/board/socrates/tlb.c
+++ b/board/socrates/tlb.c
@@ -41,7 +41,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
         * TLB 2:       256M    Non-cacheable, guarded
         * 0x80000000   256M    PCI1 MEM First half
         */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
+       SET_TLB_ENTRY(1, CFG_SYS_PCI1_MEM_PHYS, CFG_SYS_PCI1_MEM_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 2, BOOKE_PAGESZ_256M, 1),
 
@@ -49,7 +49,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
         * TLB 3:       256M    Non-cacheable, guarded
         * 0x90000000   256M    PCI1 MEM Second half
         */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+       SET_TLB_ENTRY(1, CFG_SYS_PCI1_MEM_PHYS + 0x10000000, CFG_SYS_PCI1_MEM_PHYS + 0x10000000,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                      0, 3, BOOKE_PAGESZ_256M, 1),
 

diff --git a/common/fdt_support.c b/common/fdt_support.c
index ebebffc789043c0271f78346bc2ba00b679750bd..dbceec6f2dcc00e4d8c3e4829fa61f4cdb1f6fea 100644 (file)
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -739,7 +739,7 @@ int fdt_delete_disabled_nodes(void *blob)
 }
 
 #ifdef CONFIG_PCI
-#define CONFIG_SYS_PCI_NR_INBOUND_WIN 4
+#define CFG_SYS_PCI_NR_INBOUND_WIN 4
 
 #define FDT_PCI_PREFETCH       (0x40000000)
 #define FDT_PCI_MEM32          (0x02000000)
@@ -751,7 +751,7 @@ int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose) {
        int addrcell, sizecell, len, r;
        u32 *dma_range;
        /* sized based on pci addr cells, size-cells, & address-cells */
-       u32 dma_ranges[(3 + 2 + 2) * CONFIG_SYS_PCI_NR_INBOUND_WIN];
+       u32 dma_ranges[(3 + 2 + 2) * CFG_SYS_PCI_NR_INBOUND_WIN];
 
        addrcell = fdt_getprop_u32_default(blob, "/", "#address-cells", 1);
        sizecell = fdt_getprop_u32_default(blob, "/", "#size-cells", 1);

diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index c7968926a17fc3ebf0c6bd7eb59d10c27bc87a6c..14fd3bbf679e74a2e2662ef6f5d33a16999797d4 100644 (file)
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -16,9 +16,9 @@
 #include <time.h>
 #include "pci_internal.h"
 
-/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
-#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
-#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
+/* the user can define CFG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
+#ifndef CFG_SYS_PCI_CACHE_LINE_SIZE
+#define CFG_SYS_PCI_CACHE_LINE_SIZE    8
 #endif
 
 static void dm_pciauto_setup_device(struct udevice *dev,
@@ -178,7 +178,7 @@ static void dm_pciauto_setup_device(struct udevice *dev,
 
        dm_pci_write_config16(dev, PCI_COMMAND, cmdstat);
        dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE,
-                            CONFIG_SYS_PCI_CACHE_LINE_SIZE);
+                            CFG_SYS_PCI_CACHE_LINE_SIZE);
        dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80);
 }
 

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index a8f8c31bef8fe9e3f02baf7d5487d0853ab6034b..4600652f2b1b4f5e988d1f9b7f0811a47f11124c 100644 (file)
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -343,8 +343,8 @@ static int fsl_pcie_setup_outbound_wins(struct fsl_pcie *pcie)
 
 static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie)
 {
-       phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
-       pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
+       phys_addr_t phys_start = CFG_SYS_PCI_MEMORY_PHYS;
+       pci_addr_t bus_start = CFG_SYS_PCI_MEMORY_BUS;
        u64 sz = min((u64)gd->ram_size, (1ull << 32));
        pci_size_t pci_sz;
        int idx;
@@ -367,8 +367,8 @@ static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie)
                sz = 2ull << __ilog2_u64(sz);
 
        fsl_pcie_setup_inbound_win(pcie, idx--, true,
-                                  CONFIG_SYS_PCI_MEMORY_PHYS,
-                                  CONFIG_SYS_PCI_MEMORY_BUS, sz);
+                                  CFG_SYS_PCI_MEMORY_PHYS,
+                                  CFG_SYS_PCI_MEMORY_BUS, sz);
 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
        /*
         * On 64-bit capable systems, set up a mapping for all of DRAM
@@ -380,12 +380,12 @@ static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie)
                pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
 
        dev_dbg(pcie->bus, "R64 bus_start: %llx phys_start: %llx size: %llx\n",
-               (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
-               (u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz);
+               (u64)CFG_SYS_PCI64_MEMORY_BUS,
+               (u64)CFG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz);
 
        fsl_pcie_setup_inbound_win(pcie, idx--, true,
-                                  CONFIG_SYS_PCI_MEMORY_PHYS,
-                                  CONFIG_SYS_PCI64_MEMORY_BUS, pci_sz);
+                                  CFG_SYS_PCI_MEMORY_PHYS,
+                                  CFG_SYS_PCI64_MEMORY_BUS, pci_sz);
 #endif
 
        return 0;

diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h
index 70c5f4e4cffe66f0e39d3fa83fda2825ff4a08b6..ba84a232b83526bccd2922af9ee19b838f6585a2 100644 (file)
--- a/drivers/pci/pcie_fsl.h
+++ b/drivers/pci/pcie_fsl.h
@@ -28,16 +28,16 @@
 
 #define DBI_RO_WR_EN                   0x8bc
 
-#ifndef CONFIG_SYS_PCI_MEMORY_BUS
-#define CONFIG_SYS_PCI_MEMORY_BUS      0
+#ifndef CFG_SYS_PCI_MEMORY_BUS
+#define CFG_SYS_PCI_MEMORY_BUS 0
 #endif
 
-#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
-#define CONFIG_SYS_PCI_MEMORY_PHYS     0
+#ifndef CFG_SYS_PCI_MEMORY_PHYS
+#define CFG_SYS_PCI_MEMORY_PHYS        0
 #endif
 
-#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
-#define CONFIG_SYS_PCI64_MEMORY_BUS    (64ull * 1024 * 1024 * 1024)
+#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CFG_SYS_PCI64_MEMORY_BUS)
+#define CFG_SYS_PCI64_MEMORY_BUS       (64ull * 1024 * 1024 * 1024)
 #endif
 
 #define PEX_CSR0_LTSSM_MASK            0xFC

diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index 8cdf516d9fad554ed5d2258612bbfd67f7e7eb31..a52774179e2f4967c4b0dcc39673d07b27cd822b 100644 (file)
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -13,20 +13,20 @@
 #include <asm/arch-fsl-layerscape/svr.h>
 #include <asm/arch-ls102xa/svr.h>
 
-#ifndef CONFIG_SYS_PCI_MEMORY_BUS
-#define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
+#ifndef CFG_SYS_PCI_MEMORY_BUS
+#define CFG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
 #endif
 
-#ifndef CONFIG_SYS_PCI_MEMORY_PHYS
-#define CONFIG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE
+#ifndef CFG_SYS_PCI_MEMORY_PHYS
+#define CFG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE
 #endif
 
-#ifndef CONFIG_SYS_PCI_MEMORY_SIZE
-#define CONFIG_SYS_PCI_MEMORY_SIZE SZ_4G
+#ifndef CFG_SYS_PCI_MEMORY_SIZE
+#define CFG_SYS_PCI_MEMORY_SIZE SZ_4G
 #endif
 
-#ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE
-#define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR
+#ifndef CFG_SYS_PCI_EP_MEMORY_BASE
+#define CFG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR
 #endif
 
 #define PCIE_PHYS_SIZE                 0x200000000

diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index f2813aeef67dcf88d38e01bc446a3a2e457e10c4..ff26a5cd9beed8bc8dce5b3a797115845089c10d 100644 (file)
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -72,7 +72,7 @@ static void ls_pcie_ep_setup_atu(struct ls_pcie_ep *pcie_ep, u32 pf)
        u32 vf_flag = 0;
        u64 phys = 0;
 
-       phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + pf * SZ_64M;
+       phys = CFG_SYS_PCI_EP_MEMORY_BASE + pf * SZ_64M;
 
        phys = ALIGN(phys, PCIE_BAR0_SIZE);
        /* ATU 0 : INBOUND : map BAR0 */
@@ -117,8 +117,8 @@ static void ls_pcie_ep_setup_atu(struct ls_pcie_ep *pcie_ep, u32 pf)
        /* ATU: OUTBOUND : map MEM */
        ls_pcie_atu_outbound_set(pcie, pf, PCIE_ATU_TYPE_MEM,
                                 (u64)pcie_ep->addr_res.start +
-                                pf * CONFIG_SYS_PCI_MEMORY_SIZE,
-                                0, CONFIG_SYS_PCI_MEMORY_SIZE);
+                                pf * CFG_SYS_PCI_MEMORY_SIZE,
+                                0, CFG_SYS_PCI_MEMORY_SIZE);
 }
 
 /* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */

diff --git a/drivers/pci/pcie_layerscape_gen4.c b/drivers/pci/pcie_layerscape_gen4.c
index 6ecdd6af408c8ff13cd5206a2f343a2e67b0e490..021c975869fd5c8be73d1b06bd5b3710c84638aa 100644 (file)
--- a/drivers/pci/pcie_layerscape_gen4.c
+++ b/drivers/pci/pcie_layerscape_gen4.c
@@ -333,7 +333,7 @@ static void ls_pcie_g4_ep_setup_wins(struct ls_pcie_g4 *pcie, int pf)
        if ((!pcie->sriov_support && pf > LS_G4_PF0) || pf > LS_G4_PF1)
                return;
 
-       phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR_SIZE * 4 * pf;
+       phys = CFG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR_SIZE * 4 * pf;
        for (bar = 0; bar < PF_BAR_NUM; bar++) {
                ls_pcie_g4_ep_inbound_win_set(pcie, pf, bar, phys);
                phys += PCIE_BAR_SIZE;
@@ -342,8 +342,8 @@ static void ls_pcie_g4_ep_setup_wins(struct ls_pcie_g4 *pcie, int pf)
        /* OUTBOUND: map MEM */
        ls_pcie_g4_outbound_win_set(pcie, pf, PAB_AXI_TYPE_MEM,
                                    pcie->cfg_res.start +
-                                   CONFIG_SYS_PCI_MEMORY_SIZE * pf, 0x0,
-                                   CONFIG_SYS_PCI_MEMORY_SIZE);
+                                   CFG_SYS_PCI_MEMORY_SIZE * pf, 0x0,
+                                   CFG_SYS_PCI_MEMORY_SIZE);
 
        val = ccsr_readl(pcie, PAB_AXI_AMAP_PCI_HDR_PARAM(pf));
        val &= ~FUNC_NUM_PCIE_MASK;

diff --git a/drivers/pci/pcie_layerscape_gen4.h b/drivers/pci/pcie_layerscape_gen4.h
index 483eb538b5c52a7cfee7eb4102178a92465a9212..805c23a7da0c4fcd76c8e43d9a1d960d93fca592 100644 (file)
--- a/drivers/pci/pcie_layerscape_gen4.h
+++ b/drivers/pci/pcie_layerscape_gen4.h
@@ -11,12 +11,12 @@
 #include <pci.h>
 #include <linux/bitops.h>
 
-#ifndef CONFIG_SYS_PCI_MEMORY_SIZE
-#define CONFIG_SYS_PCI_MEMORY_SIZE             (4 * 1024 * 1024 * 1024ULL)
+#ifndef CFG_SYS_PCI_MEMORY_SIZE
+#define CFG_SYS_PCI_MEMORY_SIZE                (4 * 1024 * 1024 * 1024ULL)
 #endif
 
-#ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE
-#define CONFIG_SYS_PCI_EP_MEMORY_BASE          CONFIG_SYS_LOAD_ADDR
+#ifndef CFG_SYS_PCI_EP_MEMORY_BASE
+#define CFG_SYS_PCI_EP_MEMORY_BASE             CONFIG_SYS_LOAD_ADDR
 #endif
 
 #define PCIE_PF_NUM                            2

diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 059885ecb54f76e5a9e82b56995d78cd2bce3068..0e70b2853b2913b5b54d8a2fb77c050223c2b533 100644 (file)
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -177,15 +177,15 @@
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CONFIG_SYS_PCIE1_CFG_BASE      0xA0000000
-#define CONFIG_SYS_PCIE1_CFG_SIZE      0x08000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS      0xA8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS       0xB8000000
-
-#define CONFIG_SYS_PCIE2_CFG_BASE      0xC0000000
-#define CONFIG_SYS_PCIE2_CFG_SIZE      0x08000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS      0xC8000000
-#define CONFIG_SYS_PCIE2_IO_PHYS       0xD8000000
+#define CFG_SYS_PCIE1_CFG_BASE 0xA0000000
+#define CFG_SYS_PCIE1_CFG_SIZE 0x08000000
+#define CFG_SYS_PCIE1_MEM_PHYS 0xA8000000
+#define CFG_SYS_PCIE1_IO_PHYS  0xB8000000
+
+#define CFG_SYS_PCIE2_CFG_BASE 0xC0000000
+#define CFG_SYS_PCIE2_CFG_SIZE 0x08000000
+#define CFG_SYS_PCIE2_MEM_PHYS 0xC8000000
+#define CFG_SYS_PCIE2_IO_PHYS  0xD8000000
 
 /*
  * TSEC

diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index c29e63c54ed898e66b68af5d6d9d313fe069c213..c59a37646f49a6d94f733114d19ff606a103a4f7 100644 (file)
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -254,31 +254,31 @@
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
-#define CONFIG_SYS_PCI1_MEM_VIRT       0x80000000
+#define CFG_SYS_PCI1_MEM_VIRT  0x80000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCI1_MEM_PHYS       0xc00000000ull
+#define CFG_SYS_PCI1_MEM_PHYS  0xc00000000ull
 #else
-#define CONFIG_SYS_PCI1_MEM_PHYS       0x80000000
+#define CFG_SYS_PCI1_MEM_PHYS  0x80000000
 #endif
-#define CONFIG_SYS_PCI1_IO_VIRT        0xe2000000
+#define CFG_SYS_PCI1_IO_VIRT   0xe2000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
+#define CFG_SYS_PCI1_IO_PHYS 0xfe2000000ull
 #else
-#define CONFIG_SYS_PCI1_IO_PHYS        0xe2000000
+#define CFG_SYS_PCI1_IO_PHYS   0xe2000000
 #endif
 
 #ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_MEM_VIRT      0xa0000000
+#define CFG_SYS_PCIE1_MEM_VIRT 0xa0000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_PHYS      0xc20000000ull
+#define CFG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
 #else
-#define CONFIG_SYS_PCIE1_MEM_PHYS      0xa0000000
+#define CFG_SYS_PCIE1_MEM_PHYS 0xa0000000
 #endif
-#define CONFIG_SYS_PCIE1_IO_VIRT       0xe3000000
+#define CFG_SYS_PCIE1_IO_VIRT  0xe3000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS        0xfe3000000ull
+#define CFG_SYS_PCIE1_IO_PHYS        0xfe3000000ull
 #else
-#define CONFIG_SYS_PCIE1_IO_PHYS       0xe3000000
+#define CFG_SYS_PCIE1_IO_PHYS  0xe3000000
 #endif
 #endif
 

diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index 05c097759f621059013b8e58c072d94a561f173e..f87e7597ad046f3bea358f157897ca1cb93f4a14 100644 (file)
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -68,31 +68,31 @@
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 /* controller 1, Slot 1, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT      0x80000000
+#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_PHYS      0xc00000000ull
+#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
 #else
-#define CONFIG_SYS_PCIE1_MEM_PHYS      0x80000000
+#define CFG_SYS_PCIE1_MEM_PHYS 0x80000000
 #endif
-#define CONFIG_SYS_PCIE1_IO_VIRT       0xffc00000
+#define CFG_SYS_PCIE1_IO_VIRT  0xffc00000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS       0xfffc00000ull
+#define CFG_SYS_PCIE1_IO_PHYS  0xfffc00000ull
 #else
-#define CONFIG_SYS_PCIE1_IO_PHYS       0xffc00000
+#define CFG_SYS_PCIE1_IO_PHYS  0xffc00000
 #endif
 
 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT      0xa0000000
+#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_PHYS      0xc20000000ull
+#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
 #else
-#define CONFIG_SYS_PCIE2_MEM_PHYS      0xa0000000
+#define CFG_SYS_PCIE2_MEM_PHYS 0xa0000000
 #endif
-#define CONFIG_SYS_PCIE2_IO_VIRT       0xffc10000
+#define CFG_SYS_PCIE2_IO_VIRT  0xffc10000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_IO_PHYS       0xfffc10000ull
+#define CFG_SYS_PCIE2_IO_PHYS  0xfffc10000ull
 #else
-#define CONFIG_SYS_PCIE2_IO_PHYS       0xffc10000
+#define CFG_SYS_PCIE2_IO_PHYS  0xffc10000
 #endif
 #endif
 

diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index c83298107869973bdd61a332f02caabf73e2c1c2..e996dbaa4de71537dee0c4a691cbb14680aeac63 100644 (file)
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -234,20 +234,20 @@
  */
 
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT      0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS      0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT       0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS       0xff8000000ull
+#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CFG_SYS_PCIE1_IO_VIRT  0xf8000000
+#define CFG_SYS_PCIE1_IO_PHYS  0xff8000000ull
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT      0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS      0xc20000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT       0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS       0xff8010000ull
+#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
+#define CFG_SYS_PCIE2_IO_VIRT  0xf8010000
+#define CFG_SYS_PCIE2_IO_PHYS  0xff8010000ull
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT      0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS      0xc40000000ull
+#define CFG_SYS_PCIE3_MEM_VIRT 0xc0000000
+#define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
 
 /* Qman/Bman */
 #define CONFIG_SYS_BMAN_NUM_PORTALS    10

diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index e21639a6951bcd0251325b27ad254e7aab6dd6ef..6d6e334bf00fa5a35d05f0708e28b06c201be39b 100644 (file)
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -331,24 +331,24 @@
 #ifdef CONFIG_PCI
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #ifdef CONFIG_PCIE1
-#define        CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
-#define        CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT       0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS       0xff8000000ull
+#define        CFG_SYS_PCIE1_MEM_VIRT  0x80000000
+#define        CFG_SYS_PCIE1_MEM_PHYS  0xc00000000ull
+#define CFG_SYS_PCIE1_IO_VIRT  0xf8000000
+#define CFG_SYS_PCIE1_IO_PHYS  0xff8000000ull
 #endif
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #ifdef CONFIG_PCIE2
-#define CONFIG_SYS_PCIE2_MEM_VIRT      0x90000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS      0xc10000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT       0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS       0xff8010000ull
+#define CFG_SYS_PCIE2_MEM_VIRT 0x90000000
+#define CFG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
+#define CFG_SYS_PCIE2_IO_VIRT  0xf8010000
+#define CFG_SYS_PCIE2_IO_PHYS  0xff8010000ull
 #endif
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #ifdef CONFIG_PCIE3
-#define CONFIG_SYS_PCIE3_MEM_VIRT      0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS      0xc20000000ull
+#define CFG_SYS_PCIE3_MEM_VIRT 0xa0000000
+#define CFG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
 #endif
 #endif /* CONFIG_PCI */
 

diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index a3d04882f0d6f54fb12bf8cc495c9dfcee10c701..423ba8161702ace6a7daca11672ff2294bf1c365 100644 (file)
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -307,30 +307,30 @@
 #ifdef CONFIG_PCI
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #ifdef CONFIG_PCIE1
-#define        CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
-#define        CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT       0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS       0xff8000000ull
+#define        CFG_SYS_PCIE1_MEM_VIRT  0x80000000
+#define        CFG_SYS_PCIE1_MEM_PHYS  0xc00000000ull
+#define CFG_SYS_PCIE1_IO_VIRT  0xf8000000
+#define CFG_SYS_PCIE1_IO_PHYS  0xff8000000ull
 #endif
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #ifdef CONFIG_PCIE2
-#define CONFIG_SYS_PCIE2_MEM_VIRT      0x90000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS      0xc10000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT       0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS       0xff8010000ull
+#define CFG_SYS_PCIE2_MEM_VIRT 0x90000000
+#define CFG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
+#define CFG_SYS_PCIE2_IO_VIRT  0xf8010000
+#define CFG_SYS_PCIE2_IO_PHYS  0xff8010000ull
 #endif
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #ifdef CONFIG_PCIE3
-#define CONFIG_SYS_PCIE3_MEM_VIRT      0xa0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS      0xc20000000ull
+#define CFG_SYS_PCIE3_MEM_VIRT 0xa0000000
+#define CFG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
 #endif
 
 /* controller 4, Base address 203000 */
 #ifdef CONFIG_PCIE4
-#define CONFIG_SYS_PCIE4_MEM_VIRT      0xb0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS      0xc30000000ull
+#define CFG_SYS_PCIE4_MEM_VIRT 0xb0000000
+#define CFG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
 #endif
 #endif /* CONFIG_PCI */
 

diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 72052be78a92ce6c3ef7888cc6b057b06aff8fb7..2efc2eb95c47b3485791e0ec539b93215b8ed8f0 100644 (file)
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -345,24 +345,24 @@
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT      0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS      0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT       0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS       0xff8000000ull
+#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CFG_SYS_PCIE1_IO_VIRT  0xf8000000
+#define CFG_SYS_PCIE1_IO_PHYS  0xff8000000ull
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT      0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS      0xc20000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT       0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS       0xff8010000ull
+#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
+#define CFG_SYS_PCIE2_IO_VIRT  0xf8010000
+#define CFG_SYS_PCIE2_IO_PHYS  0xff8010000ull
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT      0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS      0xc30000000ull
+#define CFG_SYS_PCIE3_MEM_VIRT 0xb0000000
+#define CFG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
 
 /* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS      0xc40000000ull
+#define CFG_SYS_PCIE4_MEM_VIRT       0xc0000000
+#define CFG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
 
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN

diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index c798e4487a4d0bacebef21cfe220868f648379b7..ca8bfac0c69d58fd0a29da4e93135ae049ca308e 100644 (file)
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -299,24 +299,24 @@
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT      0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS      0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT       0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS       0xff8000000ull
+#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CFG_SYS_PCIE1_IO_VIRT  0xf8000000
+#define CFG_SYS_PCIE1_IO_PHYS  0xff8000000ull
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT      0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS      0xc20000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT       0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS       0xff8010000ull
+#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
+#define CFG_SYS_PCIE2_IO_VIRT  0xf8010000
+#define CFG_SYS_PCIE2_IO_PHYS  0xff8010000ull
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT      0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS      0xc30000000ull
+#define CFG_SYS_PCIE3_MEM_VIRT 0xb0000000
+#define CFG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
 
 /* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS      0xc40000000ull
+#define CFG_SYS_PCIE4_MEM_VIRT       0xc0000000
+#define CFG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
 
 /* Qman/Bman */
 #ifndef CONFIG_NOBQFMAN

diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index 5777df8e5076b112321769c3edb399e4d9d87830..091920dccfe62a26ccd9516b66cb88da3a1a63fe 100644 (file)
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -107,24 +107,24 @@
  */
 
 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT      0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS      0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT       0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS       0xff8000000ull
+#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
+#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
+#define CFG_SYS_PCIE1_IO_VIRT  0xf8000000
+#define CFG_SYS_PCIE1_IO_PHYS  0xff8000000ull
 
 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT      0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS      0xc20000000ull
-#define CONFIG_SYS_PCIE2_IO_VIRT       0xf8010000
-#define CONFIG_SYS_PCIE2_IO_PHYS       0xff8010000ull
+#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000
+#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
+#define CFG_SYS_PCIE2_IO_VIRT  0xf8010000
+#define CFG_SYS_PCIE2_IO_PHYS  0xff8010000ull
 
 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT      0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS      0xc40000000ull
+#define CFG_SYS_PCIE3_MEM_VIRT 0xc0000000
+#define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
 
 /* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_BUS       0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS      0xc60000000ull
+#define CFG_SYS_PCIE4_MEM_BUS  0xe0000000
+#define CFG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
 
 /*
  * Miscellaneous configurable options

diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h
index 7af65737ff01630da5be59a78911ab1289efd653..1df90def6733989e0f8cc56087cb6e80c7df0342 100644 (file)
--- a/include/configs/kmcent2.h
+++ b/include/configs/kmcent2.h
@@ -346,10 +346,10 @@ int get_scl(void);
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 /* controller 1 */
-#define        CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
-#define        CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
-#define CONFIG_SYS_PCIE1_IO_VIRT       0xf8000000
-#define CONFIG_SYS_PCIE1_IO_PHYS       0xff8000000ull
+#define        CFG_SYS_PCIE1_MEM_VIRT  0x80000000
+#define        CFG_SYS_PCIE1_MEM_PHYS  0xc00000000ull
+#define CFG_SYS_PCIE1_IO_VIRT  0xf8000000
+#define CFG_SYS_PCIE1_IO_PHYS  0xff8000000ull
 
 #define CONFIG_SYS_BMAN_NUM_PORTALS    10
 #define CONFIG_SYS_BMAN_MEM_BASE       0xf4000000

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 44e608536fe82deaad508e6bd9b3005701f2b75e..6e8ac1b98df5e4b8dfd3b57cbbd7c596cea315a9 100644 (file)
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -343,31 +343,31 @@
  */
 
 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT      0xa0000000
+#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_PHYS      0xc20000000ull
+#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
 #else
-#define CONFIG_SYS_PCIE2_MEM_PHYS      0xa0000000
+#define CFG_SYS_PCIE2_MEM_PHYS 0xa0000000
 #endif
-#define CONFIG_SYS_PCIE2_IO_VIRT       0xffc10000
+#define CFG_SYS_PCIE2_IO_VIRT  0xffc10000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_IO_PHYS       0xfffc10000ull
+#define CFG_SYS_PCIE2_IO_PHYS  0xfffc10000ull
 #else
-#define CONFIG_SYS_PCIE2_IO_PHYS       0xffc10000
+#define CFG_SYS_PCIE2_IO_PHYS  0xffc10000
 #endif
 
 /* controller 1, Slot 2, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT      0x80000000
+#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_PHYS      0xc00000000ull
+#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
 #else
-#define CONFIG_SYS_PCIE1_MEM_PHYS      0x80000000
+#define CFG_SYS_PCIE1_MEM_PHYS 0x80000000
 #endif
-#define CONFIG_SYS_PCIE1_IO_VIRT       0xffc00000
+#define CFG_SYS_PCIE1_IO_VIRT  0xffc00000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS       0xfffc00000ull
+#define CFG_SYS_PCIE1_IO_PHYS  0xfffc00000ull
 #else
-#define CONFIG_SYS_PCIE1_IO_PHYS       0xffc00000
+#define CFG_SYS_PCIE1_IO_PHYS  0xffc00000
 #endif
 #endif /* CONFIG_PCI */
 

diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index 9b106fc1c97ea06ed268e8f4936eff7a0e4849e9..a60ac6d1a3c57d36a40159f3874a98d24540ef42 100644 (file)
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -109,8 +109,8 @@
  * Memory space is mapped 1-1.
  */
 
-#define CONFIG_SYS_PCI1_MEM_PHYS       0x80000000
-#define CONFIG_SYS_PCI1_IO_PHYS        0xE2000000
+#define CFG_SYS_PCI1_MEM_PHYS  0x80000000
+#define CFG_SYS_PCI1_IO_PHYS   0xE2000000
 
 #define CONFIG_TSEC1   1
 #define CONFIG_TSEC1_NAME      "TSEC0"