arm: mach-snapdragon: pinctrl: clarify gpio disable bit

The TLMM_GPIO_ENABLE bit is actually use to disable
the GPIO. change it to TLMM_GPIO_DISABLE so it's clearer.

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>

diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
index ac511d9ee51c98945c0d854ab984b0f67e465f69..9ba8fdd7293a1b6a31f04b3d28e3d270d3d5f949 100644 (file)
--- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
+++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
@@ -22,7 +22,7 @@ struct msm_pinctrl_priv {
 #define TLMM_GPIO_PULL_MASK GENMASK(1, 0)
 #define TLMM_FUNC_SEL_MASK GENMASK(5, 2)
 #define TLMM_DRV_STRENGTH_MASK GENMASK(8, 6)
-#define TLMM_GPIO_ENABLE BIT(9)
+#define TLMM_GPIO_DISABLE BIT(9)
 
 static const struct pinconf_param msm_conf_params[] = {
        { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 3 },
@@ -74,7 +74,7 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector,
        struct msm_pinctrl_priv *priv = dev_get_priv(dev);
 
        clrsetbits_le32(priv->base + GPIO_CONFIG_OFFSET(pin_selector),
-                       TLMM_FUNC_SEL_MASK | TLMM_GPIO_ENABLE,
+                       TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE,
                        priv->data->get_function_mux(func_selector) << 2);
        return 0;
 }