- Enable hw_watchdog_init() in watchdog.h if CONFIG_HW_WATCHDOG is defined.
- Move blackfin hw watchdog driver to the generic driver folder.
- Call hw_watchdog_init() from blackfin board init code.
- Reuse macro CONFIG_WATCHDOG_TIMEOUT_MSECS
- Update README.watchdog accordingly
Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
COBJS-y += reset.o
COBJS-y += serial.o
COBJS-y += traps.o
-COBJS-$(CONFIG_HW_WATCHDOG) += watchdog.o
SRCS := $(SEXTRA:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS))
#include <config.h>
#include <asm/blackfin.h>
+#include <asm/mach-common/bits/watchdog.h>
#include <asm/mach-common/bits/bootrom.h>
#include <asm/mach-common/bits/core.h>
bfin_write_SEC_GCTL(0x1);
bfin_write_SEC_CCTL(0x1);
#endif
+ bfin_write_WDOG_CTL(WDDIS);
+ SSYNC();
bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
#if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART
- bfin_write_WDOG_CTL(0);
+ bfin_write_WDOG_CTL(WDEN);
#endif
serial_putc('f');
}
#include <config.h>
#include <asm/blackfin.h>
+#include <asm/mach-common/bits/watchdog.h>
#include <asm/mach-common/bits/core.h>
#include <asm/mach-common/bits/pll.h>
p5.h = HI(COREMMR_BASE);
#ifdef CONFIG_HW_WATCHDOG
-#ifndef __ADSPBF60x__
-# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_START
-# define CONFIG_HW_WATCHDOG_TIMEOUT_START 5000
-# endif
- /* Program the watchdog with an initial timeout of ~5 seconds.
+ /* Program the watchdog with default timeout of ~5 seconds.
* That should be long enough to bootstrap ourselves up and
* then the common u-boot code can take over.
*/
+ r1 = WDDIS;
+# ifdef __ADSPBF60x__
+ [p4 + (WDOG_CTL - SYSMMR_BASE)] = r1;
+# else
+ W[p4 + (WDOG_CTL - SYSMMR_BASE)] = r1;
+# endif
+ SSYNC;
r0 = 0;
- r0.h = HI(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_START));
+ r0.h = HI(MSEC_TO_SCLK(CONFIG_WATCHDOG_TIMEOUT_MSECS));
[p4 + (WDOG_CNT - SYSMMR_BASE)] = r0;
+ SSYNC;
+ r1 = WDEN;
/* fire up the watchdog - R0.L above needs to be 0x0000 */
- W[p4 + (WDOG_CTL - SYSMMR_BASE)] = r0;
-#endif
+# ifdef __ADSPBF60x__
+ [p4 + (WDOG_CTL - SYSMMR_BASE)] = r1;
+# else
+ W[p4 + (WDOG_CTL - SYSMMR_BASE)] = r1;
+# endif
+ SSYNC;
#endif
/* Turn on the serial for debugging the init process */
dcache_enable();
#endif
-#ifdef CONFIG_WATCHDOG
+#ifdef CONFIG_HW_WATCHDOG
serial_early_puts("Setting up external watchdog\n");
- watchdog_init();
+ hw_watchdog_init();
#endif
#ifdef DEBUG
CONFIG_XILINX_TB_WATCHDOG
Available for Xilinx Axi platforms to service timebase watchdog timer.
+
+CONFIG_BFIN_WATCHDOG
+ Available for bf5xx and bf6xx to service the watchdog.
COBJS-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o
COBJS-$(CONFIG_S5P) += s5p_wdt.o
COBJS-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
+COBJS-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
#include <common.h>
#include <watchdog.h>
#include <asm/blackfin.h>
+#include <asm/mach-common/bits/watchdog.h>
void hw_watchdog_reset(void)
{
void hw_watchdog_init(void)
{
- bfin_write_WDOG_CNT(5 * get_sclk()); /* 5 second timeout */
+ bfin_write_WDOG_CTL(WDDIS);
+ SSYNC();
+ bfin_write_WDOG_CNT(CONFIG_WATCHDOG_TIMEOUT_MSECS / 1000 * get_sclk());
hw_watchdog_reset();
- bfin_write_WDOG_CTL(0x0);
+ bfin_write_WDOG_CTL(WDEN);
}
#define CONFIG_BFIN_SPI_GPIO_CS /* Only matters if BFIN_SPI is enabled */
#define CONFIG_LZMA
#define CONFIG_MONITOR_IS_IN_RAM
+#ifdef CONFIG_HW_WATCHDOG
+# define CONFIG_BFIN_WATCHDOG
+# ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
+# define CONFIG_WATCHDOG_TIMEOUT_MSECS 5000
+# endif
+#endif
#endif
void reset_4xx_watchdog(void);
#endif
-/* Freescale i.MX */
-#if defined(CONFIG_IMX_WATCHDOG) && !defined(__ASSEMBLY__)
+#if defined(CONFIG_HW_WATCHDOG) && !defined(__ASSEMBLY__)
void hw_watchdog_init(void);
#endif
#endif /* _WATCHDOG_H_ */