F: arch/arm/cpu/armv8/hisilicon
F: arch/arm/include/asm/arch-hi6220/
F: arch/arm/include/asm/arch-hi3660/
+F: arch/arm/mach-histb
ARM HPE GXP ARCHITECTURE
M: Jean-Marie Verdun <verdun@hpe.com>
help
Support for TI's DaVinci platform.
+config ARCH_HISTB
+ bool "Hisilicon HiSTB SoCs"
+ select DM
+ select DM_SERIAL
+ select OF_CONTROL
+ select PL01X_SERIAL
+ imply CMD_DM
+ help
+ Support for HiSTB SoCs.
+
config ARCH_KIRKWOOD
bool "Marvell Kirkwood"
select ARCH_MISC_INIT
source "arch/arm/mach-highbank/Kconfig"
+source "arch/arm/mach-histb/Kconfig"
+
source "arch/arm/mach-integrator/Kconfig"
source "arch/arm/mach-ipq40xx/Kconfig"
machine-$(CONFIG_ARCH_EXYNOS) += exynos
machine-$(CONFIG_ARCH_GXP) += hpe
machine-$(CONFIG_ARCH_HIGHBANK) += highbank
+machine-$(CONFIG_ARCH_HISTB) += histb
machine-$(CONFIG_ARCH_IPQ40XX) += ipq40xx
machine-$(CONFIG_ARCH_K3) += k3
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
--- /dev/null
+if ARCH_HISTB
+
+choice
+ prompt "Select a HiSTB SoC"
+
+config ARCH_HI3798MV2X
+ bool "Hi3798M V2XX series SoC"
+ select ARM64
+ help
+ Support for Hi3798MV2XX series SoCs.
+
+endchoice
+
+endif
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += sysmap-histb.o
+obj-y += board_common.o
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board init file for all histb boards
+ *
+ * (C) Copyright 2023 Yang Xiwen <forbidden405@outlook.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <asm/system.h>
+
+int __weak board_init(void)
+{
+ return 0;
+}
+
+int __weak dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+int __weak dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+void __weak reset_cpu(void)
+{
+ psci_system_reset();
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Hisilicon HiSTB memory map
+ *
+ * (C) Copyright 2023 Yang Xiwen <forbidden405@outlook.com>
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region histb_mem_map[] = {
+ {
+ .virt = 0x0UL, /* DRAM */
+ .phys = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x80000000UL, /* Peripheral block */
+ .phys = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* Terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = histb_mem_map;