]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
ARM: dts: dra7x: Support QSPI MODE-0 operation at 64MHz
authorVignesh R <vigneshr@ti.com>
Wed, 6 Jul 2016 04:56:03 +0000 (10:26 +0530)
committerJagan Teki <jteki@openedev.com>
Sat, 9 Jul 2016 14:46:33 +0000 (20:16 +0530)
According to Data Manual(SPRS915P) of AM57x, TI QSPI controller on
DRA74(rev 1.1+)/DRA72 EVM can support up to 64MHz in MODE-0, whereas
MODE-3 is limited to 48MHz. Hence, switch to MODE-0 for better
throughput.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
arch/arm/dts/dra7-evm.dts
arch/arm/dts/dra72-evm.dts

index 08ef04e177b038bb500b4b134d783788fba0ab4b..429b9edc1b2b4f547fa844a92a97e0fa4123003f 100644 (file)
        pinctrl-names = "default";
        pinctrl-0 = <&qspi1_pins>;
 
-       spi-max-frequency = <48000000>;
+       spi-max-frequency = <64000000>;
        m25p80@0 {
                compatible = "s25fl256s1","spi-flash";
-               spi-max-frequency = <48000000>;
+               spi-max-frequency = <64000000>;
                reg = <0>;
                spi-tx-bus-width = <1>;
                spi-rx-bus-width = <4>;
-               spi-cpol;
-               spi-cpha;
                #address-cells = <1>;
                #size-cells = <1>;
 
index 205103e2b0e1ab0a62096bb055ae1f2d4a13d106..ced2f1166d8c2ddb5d57e33fcf853a91daf9cf5e 100644 (file)
        pinctrl-names = "default";
        pinctrl-0 = <&qspi1_pins>;
 
-       spi-max-frequency = <48000000>;
+       spi-max-frequency = <64000000>;
        m25p80@0 {
                compatible = "s25fl256s1","spi-flash";
-               spi-max-frequency = <48000000>;
+               spi-max-frequency = <64000000>;
                reg = <0>;
                spi-tx-bus-width = <1>;
                spi-rx-bus-width = <4>;
-               spi-cpol;
-               spi-cpha;
                #address-cells = <1>;
                #size-cells = <1>;