86xx: Rename ccsr_ddr's sdram_mode_1, sdram_cfg_1 fields

Rename sdram_mode_1 to sdram_mode and sdram_cfg_1 to sdram_cfg to match
the 86xx user's manual and other Freescale architectures

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index a85ebead5f8f51e5d909c3826ef23693f42177cb..419b2c191eb87d2606b428f252b98c87e2dcb984 100644 (file)
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -154,7 +154,7 @@ phys_size_t fixed_sdram(void)
        ddr->timing_cfg_0 = 0x00260802;
        ddr->timing_cfg_1 = 0x3935d322;
        ddr->timing_cfg_2 = 0x14904cc8;
-       ddr->sdram_mode_1 = 0x00480432;
+       ddr->sdram_mode = 0x00480432;
        ddr->sdram_mode_2 = 0x00000000;
        ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
        ddr->sdram_data_init = 0xDEADBEEF;
@@ -170,7 +170,7 @@ phys_size_t fixed_sdram(void)
 
        udelay(500);
 
-       ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/
+       ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
 
 
 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)

diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index 441127bbf5c77a02c7743c0c3c5b62f031f89db0..ce26320781201e2defd03a4ea889aa85f077a360 100644 (file)
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -101,7 +101,7 @@ fixed_sdram(void)
        ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
        ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
        ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-       ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1;
+       ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
        ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
        ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
        ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
@@ -119,9 +119,9 @@ fixed_sdram(void)
 
 #if defined (CONFIG_DDR_ECC)
        /* Enable ECC checking */
-       ddr->sdram_cfg_1 = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
+       ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
 #else
-       ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CONTROL;
+       ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
        ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 #endif
        asm("sync; isync");

diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
index c39d2c020c6d83315b2eaba5d03f4e91fa2d11c9..f118a6eaa6a175874c8074e95eeacc7505da9719 100644 (file)
--- a/board/sbc8641d/sbc8641d.c
+++ b/board/sbc8641d/sbc8641d.c
@@ -127,9 +127,9 @@ long int fixed_sdram (void)
        ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
        ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
        ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
-       ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1A;
+       ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
        ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
-       ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1;
+       ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
        ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
        ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL;
        ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
@@ -140,7 +140,7 @@ long int fixed_sdram (void)
 
        udelay (500);
 
-       ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1B;
+       ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
        asm ("sync; isync");
 
        udelay (500);
@@ -158,9 +158,9 @@ long int fixed_sdram (void)
        ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
        ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
        ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
-       ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1A;
+       ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
        ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
-       ddr->sdram_mode_1 = CONFIG_SYS_DDR2_MODE_1;
+       ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
        ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
        ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL;
        ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
@@ -171,7 +171,7 @@ long int fixed_sdram (void)
 
        udelay (500);
 
-       ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1B;
+       ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
        asm ("sync; isync");
 
        udelay (500);

diff --git a/cpu/mpc86xx/ddr-8641.c b/cpu/mpc86xx/ddr-8641.c
index 51d0102ce1e780f478302daea4c8d6210ff59b55..b8f2c9387f591ba70d54f825e7f14763c21d01db 100644 (file)
--- a/cpu/mpc86xx/ddr-8641.c
+++ b/cpu/mpc86xx/ddr-8641.c
@@ -56,7 +56,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
        out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
        out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
-       out_be32(&ddr->sdram_mode_1, regs->ddr_sdram_mode);
+       out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
        out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
        out_be32(&ddr->sdram_mode_cntl, regs->ddr_sdram_md_cntl);
        out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
@@ -74,7 +74,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        udelay(200);
        asm volatile("sync;isync");
 
-       out_be32(&ddr->sdram_cfg_1, regs->ddr_sdram_cfg);
+       out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
 
        /*
         * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done

diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
index a8398348b1e923dc1e5286ea64f621770965708d..fdfc654f294b31c2e71e27822e74c0add0fd0f8f 100644 (file)
--- a/include/asm-ppc/immap_86xx.h
+++ b/include/asm-ppc/immap_86xx.h
@@ -114,9 +114,9 @@ typedef struct ccsr_ddr {
        uint    timing_cfg_0;           /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */
        uint    timing_cfg_1;           /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
        uint    timing_cfg_2;           /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
-       uint    sdram_cfg_1;            /* 0x2110 - DDR SDRAM Control Configuration 1 */
+       uint    sdram_cfg;              /* 0x2110 - DDR SDRAM Control Configuration 1 */
        uint    sdram_cfg_2;            /* 0x2114 - DDR SDRAM Control Configuration 2 */
-       uint    sdram_mode_1;           /* 0x2118 - DDR SDRAM Mode Configuration 1 */
+       uint    sdram_mode;             /* 0x2118 - DDR SDRAM Mode Configuration 1 */
        uint    sdram_mode_2;           /* 0x211c - DDR SDRAM Mode Configuration 2 */
        uint    sdram_mode_cntl;        /* 0x2120 - DDR SDRAM Mode Control */
        uint    sdram_interval;         /* 0x2124 - DDR SDRAM Interval Configuration */