ARM: tegra30: clock: implement PLLD2 support

PLLD2 is a simple clock (controlled by 2 registers) and appears starting
from T30. Primary use of PLLD2 is as main HDMI clock parent.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>

diff --git a/arch/arm/include/asm/arch-tegra/clk_rst.h b/arch/arm/include/asm/arch-tegra/clk_rst.h
index 2359e142fb7f564863b253bd5f140d6156209bf3..04910d594ebb190361ea0690a9ef96b29aaf5917 100644 (file)
--- a/arch/arm/include/asm/arch-tegra/clk_rst.h
+++ b/arch/arm/include/asm/arch-tegra/clk_rst.h
@@ -174,8 +174,7 @@ struct clk_rst_ctlr {
        uint crc_audio_sync_clk_i2s4;   /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */
        uint crc_audio_sync_clk_spdif;  /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */
 
-       uint crc_plld2_base;            /* _PLLD2_BASE_0, 0x4B8 */
-       uint crc_plld2_misc;            /* _PLLD2_MISC_0, 0x4BC */
+       struct clk_pll_simple plld2;    /* _PLLD2_BASE_0, 0x4B8 */
        uint crc_utmip_pll_cfg3;        /* _UTMIP_PLL_CFG3_0, 0x4C0 */
        uint crc_pllrefe_base;          /* _PLLREFE_BASE_0, 0x4C4 */
        uint crc_pllrefe_misc;          /* _PLLREFE_MISC_0, 0x4C8 */

diff --git a/arch/arm/include/asm/arch-tegra30/clock-tables.h b/arch/arm/include/asm/arch-tegra30/clock-tables.h
index 6c899ff64c8c8b1f477951e5a5a75b5564286939..5ebcbc2c9ad62ecb5a54f6f8770ca920850d9aa7 100644 (file)
--- a/arch/arm/include/asm/arch-tegra30/clock-tables.h
+++ b/arch/arm/include/asm/arch-tegra30/clock-tables.h
@@ -23,6 +23,7 @@ enum clock_id {
        CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
        CLOCK_ID_EPCI,
        CLOCK_ID_SFROM32KHZ,
+       CLOCK_ID_DISPLAY2,
 
        /* These are the base clocks (inputs to the Tegra SOC) */
        CLOCK_ID_32KHZ,
@@ -30,7 +31,6 @@ enum clock_id {
        CLOCK_ID_CLK_M,
 
        CLOCK_ID_COUNT, /* number of PLLs */
-       CLOCK_ID_DISPLAY2,      /* Tegra3, placeholder */
        CLOCK_ID_NONE = -1,
 };
 

diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 7f31630a2347b2bf6301337ba507e664dd1d9f31..575da2bdb5a2dc3c5a26273bf19ae7842ae31bbf 100644 (file)
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -768,6 +768,9 @@ void clock_init(void)
        pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
        pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
        pll_rate[CLOCK_ID_CLK_M] = clock_get_rate(CLOCK_ID_CLK_M);
+#ifndef CONFIG_TEGRA20
+       pll_rate[CLOCK_ID_DISPLAY2] = clock_get_rate(CLOCK_ID_DISPLAY2);
+#endif
 
        debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
        debug("CLKM = %d\n", pll_rate[CLOCK_ID_CLK_M]);

diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c
index 7bbe70921f0a393dacfffb565daaae3ec003c9a7..0af8cde8c64db419199df67a0ab77feea298a1eb 100644 (file)
--- a/arch/arm/mach-tegra/tegra30/clock.c
+++ b/arch/arm/mach-tegra/tegra30/clock.c
@@ -438,6 +438,8 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
          .lock_ena = 9,  .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 },     /* PLLE */
        { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
          .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */
+       { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
+         .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD2 */
 };
 
 /*
@@ -654,6 +656,9 @@ enum clock_id clk_id_to_pll_id(int clk_id)
        case TEGRA30_CLK_PLL_D:
        case TEGRA30_CLK_PLL_D_OUT0:
                return CLOCK_ID_DISPLAY;
+       case TEGRA30_CLK_PLL_D2:
+       case TEGRA30_CLK_PLL_D2_OUT0:
+               return CLOCK_ID_DISPLAY2;
        case TEGRA30_CLK_PLL_X:
                return CLOCK_ID_XCPU;
        case TEGRA30_CLK_PLL_E:
@@ -881,6 +886,8 @@ struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
        case CLOCK_ID_EPCI:
        case CLOCK_ID_SFROM32KHZ:
                return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE];
+       case CLOCK_ID_DISPLAY2:
+               return &clkrst->plld2;
        default:
                return NULL;
        }