ARM: k2g: Program DDRPHY_DATX8 registers via mask and value variables

Different K2G evms may need to program the various
KS2_DDRPHY_DATX8_X_OFFSET registers in different ways. Therefore, use
the mask and val registers for each KS2_DDRPHY_DATAX_X_OFFSET to
properly program the register.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c
index 25a9637c3f39b978e29f6334c7164d7ce3b846ad..4cad6a2d81c33a508f1623be9f847d81ff2874f9 100644 (file)
--- a/arch/arm/mach-keystone/ddr3.c
+++ b/arch/arm/mach-keystone/ddr3.c
@@ -65,11 +65,33 @@ void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg)
                ;
 
        if (cpu_is_k2g()) {
-               setbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1);
-               clrbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, 0x1);
-               clrbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, 0x1);
-               clrbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, 0x1);
-               clrbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET, 0x1);
+               clrsetbits_le32(base + KS2_DDRPHY_DATX8_2_OFFSET,
+                               phy_cfg->datx8_2_mask,
+                               phy_cfg->datx8_2_val);
+
+               clrsetbits_le32(base + KS2_DDRPHY_DATX8_3_OFFSET,
+                               phy_cfg->datx8_3_mask,
+                               phy_cfg->datx8_3_val);
+
+               clrsetbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET,
+                               phy_cfg->datx8_4_mask,
+                               phy_cfg->datx8_4_val);
+
+               clrsetbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET,
+                               phy_cfg->datx8_5_mask,
+                               phy_cfg->datx8_5_val);
+
+               clrsetbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET,
+                               phy_cfg->datx8_6_mask,
+                               phy_cfg->datx8_6_val);
+
+               clrsetbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET,
+                               phy_cfg->datx8_7_mask,
+                               phy_cfg->datx8_7_val);
+
+               clrsetbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET,
+                               phy_cfg->datx8_8_mask,
+                               phy_cfg->datx8_8_val);
        }
 
        __raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);

diff --git a/board/ti/ks2_evm/ddr3_k2g.c b/board/ti/ks2_evm/ddr3_k2g.c
index aeb7da6bd18a15be6436e865229a4622ee7e7bff..3b12943237b60b079f1ce217499faf5491ab9218 100644 (file)
--- a/board/ti/ks2_evm/ddr3_k2g.c
+++ b/board/ti/ks2_evm/ddr3_k2g.c
@@ -34,6 +34,20 @@ struct ddr3_phy_config ddr3phy_800_2g = {
        .zq1cr1         = 0x0001005Bul,
        .zq2cr1         = 0x0001005Bul,
        .pir_v1         = 0x00000033ul,
+       .datx8_2_mask   = 0,
+       .datx8_2_val    = 0,
+       .datx8_3_mask   = 0,
+       .datx8_3_val    = 0,
+       .datx8_4_mask   = 0,
+       .datx8_4_val    = ((1 << 0)),
+       .datx8_5_mask   = DXEN_MASK,
+       .datx8_5_val    = 0,
+       .datx8_6_mask   = DXEN_MASK,
+       .datx8_6_val    = 0,
+       .datx8_7_mask   = DXEN_MASK,
+       .datx8_7_val    = 0,
+       .datx8_8_mask   = DXEN_MASK,
+       .datx8_8_val    = 0,
        .pir_v2         = 0x00000F81ul,
 };