]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
MIPS: xburst/start.S: use t8 register for dynamic relocation
authorGabor Juhos <juhosg@openwrt.org>
Thu, 13 Jun 2013 10:59:32 +0000 (12:59 +0200)
committerTom Rini <trini@ti.com>
Wed, 24 Jul 2013 13:51:06 +0000 (09:51 -0400)
Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
arch/mips/cpu/xburst/start.S

index 6adabdc4546cd990fdb3b928eaea81cfcc23c604..e5ff4e072459091eccd8d29074065eb73f66da1c 100644 (file)
@@ -117,19 +117,19 @@ in_ram:
         * generated by GNU ld. Skip these reserved entries from relocation.
         */
        lw      t3, -4(t0)              # t3 <-- num_got_entries
-       lw      t4, -8(t0)              # t4 <-- _GLOBAL_OFFSET_TABLE_
-       add     t4, s1                  # t4 now holds relocated _G_O_T_
-       addi    t4, t4, 8               # skipping first two entries
+       lw      t8, -8(t0)              # t8 <-- _GLOBAL_OFFSET_TABLE_
+       add     t8, s1                  # t8 now holds relocated _G_O_T_
+       addi    t8, t8, 8               # skipping first two entries
        li      t2, 2
 1:
-       lw      t1, 0(t4)
+       lw      t1, 0(t8)
        beqz    t1, 2f
         add    t1, s1
-       sw      t1, 0(t4)
+       sw      t1, 0(t8)
 2:
        addi    t2, 1
        blt     t2, t3, 1b
-        addi   t4, 4
+        addi   t8, 4
 
        /* Update dynamic relocations */
        lw      t1, -16(t0)             # t1 <-- __rel_dyn_start
@@ -147,11 +147,11 @@ in_ram:
 
        lw      t3, -8(t1)              # t3 <-- location to fix up in FLASH
 
-       lw      t4, 0(t3)               # t4 <-- original pointer
-       add     t4, s1                  # t4 <-- adjusted pointer
+       lw      t8, 0(t3)               # t8 <-- original pointer
+       add     t8, s1                  # t8 <-- adjusted pointer
 
        add     t3, s1                  # t3 <-- location to fix up in RAM
-       sw      t4, 0(t3)
+       sw      t8, 0(t3)
 
 2:
        blt     t1, t2, 1b