priv->regs = regmap_get_range(map, 0);
priv->phy = regmap_get_range(map, 1);
- priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"clock-frequency", 0);
if (!priv->clock_rate) {
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3288_sdram_params *params = dev_get_platdata(dev);
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int ret;
/* Rk3288 supports dual-channel, set default channel num to 2 */
static int altera_nios2_probe(struct udevice *dev)
{
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
gd->cpu_clk = fdtdec_get_int(blob, node,
"clock-frequency", 0);
/* Set the slow ramp rate */
msr.hi &= ~(0x3 << (53 - 32));
/* Configure the C-state exit ramp rate */
- ramp = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "intel,slow-ramp",
- -1);
+ ramp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "intel,slow-ramp", -1);
if (ramp != -1) {
/* Configured slow ramp rate */
msr.hi |= ((ramp & 0x3) << (53 - 32));
}
/* Set MIN_VID (31:24) to allow CPU to have full control */
msr.lo &= ~0xff000000;
- min_vid = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "intel,min-vid",
- 0);
+ min_vid = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "intel,min-vid", 0);
msr.lo |= (min_vid & 0xff) << 24;
msr_write(MSR_VR_MISC_CONFIG, msr);
int tcc_offset;
msr_t msr;
- tcc_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ tcc_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"intel,tcc-offset", 0);
/* Set TCC activaiton offset if supported */
debug("Set power %s after power failure.\n", state);
/* GPE setup based on device tree configuration */
- ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
"intel,gpe0-en", enable, ARRAY_SIZE(enable));
if (ret)
return -EINVAL;
enable_all_gpe(enable[0], enable[1], enable[2], enable[3]);
/* SMI setup based on device tree configuration */
- enable_alt_smi(dev, fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ enable_alt_smi(dev, fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"intel,alt-gp-smi-enable", 0));
return 0;
int node;
debug("%s: starting\n", __func__);
- for (node = fdt_first_subnode(blob, dev->of_offset);
+ for (node = fdt_first_subnode(blob, dev_of_offset(dev));
node > 0;
node = fdt_next_subnode(blob, node)) {
int phandle = fdt_get_phandle(blob, node);
int count = 0;
int node;
- for (node = fdt_first_subnode(blob, dev->of_offset);
+ for (node = fdt_first_subnode(blob, dev_of_offset(dev));
node > 0;
node = fdt_next_subnode(blob, node)) {
int len, i;
{
struct sata_platdata *plat = dev_get_platdata(dev);
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
plat->port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
plat->port0_gen3_tx = fdtdec_get_int(blob, node,
struct cpu_platdata *plat = dev_get_parent_platdata(dev);
struct cpuid_result res;
- plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"intel,apic-id", -1);
plat->family = gd->arch.x86;
res = cpuid(1);
int count;
int i;
- count = fdtdec_get_int_array_count(gd->fdt_blob, dev->of_offset,
+ count = fdtdec_get_int_array_count(gd->fdt_blob, dev_of_offset(dev),
"intel,gen-dec", (u32 *)values,
sizeof(values) / sizeof(u32));
if (count < 0)
spd_index = dm_gpio_get_values_as_int(desc, ret);
debug("spd index %d\n", spd_index);
- node = fdt_first_subnode(blob, dev->of_offset);
+ node = fdt_first_subnode(blob, dev_of_offset(dev));
if (node < 0)
return -EINVAL;
for (spd_node = fdt_first_subnode(blob, node);
int i;
int ret;
- node = dev->of_offset;
+ node = dev_of_offset(dev);
/* extract the bdf from fdt_pci_addr */
priv->bdf = dm_pci_get_bdf(dev->parent);
{
uint8_t route[8], *ptr;
- if (fdtdec_get_byte_array(gd->fdt_blob, pch->of_offset,
+ if (fdtdec_get_byte_array(gd->fdt_blob, dev_of_offset(pch),
"intel,pirq-routing", route, sizeof(route)))
return -EINVAL;
ptr = route;
u32 reg;
int gpi;
- if (fdtdec_get_byte_array(gd->fdt_blob, pch->of_offset,
+ if (fdtdec_get_byte_array(gd->fdt_blob, dev_of_offset(pch),
"intel,gpi-routing", route, sizeof(route)))
return -EINVAL;
static int pch_power_options(struct udevice *pch)
{
const void *blob = gd->fdt_blob;
- int node = pch->of_offset;
+ int node = dev_of_offset(pch);
u8 reg8;
u16 reg16, pmbase;
u32 reg32;
int tcc_offset;
msr_t msr;
- tcc_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "tcc-offset",
- 0);
+ tcc_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "tcc-offset", 0);
/* Set TCC activaiton offset if supported */
msr = msr_read(MSR_PLATFORM_INFO);
{
unsigned int port_map, speed_support, port_tx;
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
const char *mode;
u32 reg32;
u16 reg16;
static void bd82x6x_sata_enable(struct udevice *dev)
{
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
unsigned port_map;
const char *mode;
u16 map = 0;
* seq num in the uclass_resolve_seq() during device_probe(). To avoid
* this, set req_seq to the reg number in the device tree in advance.
*/
- cpu->req_seq = fdtdec_get_int(gd->fdt_blob, cpu->of_offset, "reg", -1);
+ cpu->req_seq = fdtdec_get_int(gd->fdt_blob, dev_of_offset(cpu), "reg",
+ -1);
plat->ucode_version = microcode_read_rev();
plat->device_id = gd->arch.x86_device;
}
/* Get I/O interrupt information from device tree */
- cell = fdt_getprop(blob, dev->of_offset, "intel,pirq-routing", &len);
+ cell = fdt_getprop(blob, dev_of_offset(dev), "intel,pirq-routing",
+ &len);
if (!cell)
return -ENOENT;
return -EINVAL;
}
- for (pin_node = fdt_first_subnode(gd->fdt_blob, dev->of_offset);
+ for (pin_node = fdt_first_subnode(gd->fdt_blob, dev_of_offset(dev));
pin_node > 0;
pin_node = fdt_next_subnode(gd->fdt_blob, pin_node)) {
/* Configure the pin */
/* Try to request gpios needed to start usb host on dragonboard */
if (!dm_gpio_is_valid(&hub_reset)) {
- node = fdt_subnode_offset(gd->fdt_blob, pmic_gpio->of_offset,
+ node = fdt_subnode_offset(gd->fdt_blob,
+ dev_of_offset(pmic_gpio),
"usb_hub_reset_pm");
if (node < 0) {
printf("Failed to find usb_hub_reset_pm dt node.\n");
}
if (!dm_gpio_is_valid(&usb_sel)) {
- node = fdt_subnode_offset(gd->fdt_blob, pmic_gpio->of_offset,
+ node = fdt_subnode_offset(gd->fdt_blob,
+ dev_of_offset(pmic_gpio),
"usb_sw_sel_pm");
if (node < 0) {
printf("Failed to find usb_sw_sel_pm dt node.\n");
return 0;
}
- node = fdt_subnode_offset(gd->fdt_blob, pon->of_offset, "key_vol_down");
+ node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon),
+ "key_vol_down");
if (node < 0) {
printf("Failed to find key_vol_down node. Check device tree\n");
return 0;
g. If the driver provides an ofdata_to_platdata() method, then this is
called to convert the device tree data into platform data. This should
- do various calls like fdtdec_get_int(gd->fdt_blob, dev->of_offset, ...)
+ do various calls like fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), ...)
to access the node and store the resulting information into dev->platdata.
After this point, the device works the same way whether it was bound
using a device tree node or U_BOOT_DEVICE() structure. In either case,
/* Decode the device tree data */
struct mmc_platdata *plat = dev_get_platdata(dev);
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
plat->fifo_depth = fdtdec_get_int(blob, node, "fifo-depth", 0);
#endif
{
struct exynos_spi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
plat->regs = (struct exynos_spi *)fdtdec_get_addr(blob, node, "reg");
plat->periph_id = pinmux_decode_periph_id(blob, node);
static int adc_vdd_platdata_set(struct udevice *dev)
{
struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
- int ret, offset = dev->of_offset;
+ int ret, offset = dev_of_offset(dev);
const void *fdt = gd->fdt_blob;
char *prop;
static int adc_vss_platdata_set(struct udevice *dev)
{
struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
- int ret, offset = dev->of_offset;
+ int ret, offset = dev_of_offset(dev);
const void *fdt = gd->fdt_blob;
char *prop;
u32 num_parents;
num_parents = fdtdec_get_int_array_count(gd->fdt_blob,
- dev_get_parent(dev)->of_offset,
- "clocks", cells,
- GENERATED_SOURCE_MAX);
+ dev_of_offset(dev_get_parent(dev)), "clocks", cells,
+ GENERATED_SOURCE_MAX);
if (!num_parents)
return -1;
int at91_clk_sub_device_bind(struct udevice *dev, const char *drv_name)
{
const void *fdt = gd->fdt_blob;
- int offset = dev->of_offset;
+ int offset = dev_of_offset(dev);
bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC);
const char *name;
int ret;
return -EINVAL;
}
- periph = fdtdec_get_uint(gd->fdt_blob, clk->dev->of_offset, "reg", -1);
+ periph = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(clk->dev), "reg",
+ -1);
if (periph < 0)
return -EINVAL;
debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
assert(clk);
- ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
+ ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev),
"clocks", "#clock-cells", 0, index,
&args);
if (ret) {
debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk);
- index = fdt_stringlist_search(gd->fdt_blob, dev->of_offset,
+ index = fdt_stringlist_search(gd->fdt_blob, dev_of_offset(dev),
"clock-names", name);
if (index < 0) {
debug("fdt_stringlist_search() failed: %d\n", index);
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
to_clk_fixed_rate(dev)->fixed_rate =
- fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"clock-frequency", 0);
#endif
for (i = REF1CLK; i <= REF5CLK; i++) {
snprintf(propname, sizeof(propname),
"microchip,refo%d-frequency", i - REF1CLK + 1);
- rate = fdtdec_get_int(blob, dev->of_offset, propname, 0);
+ rate = fdtdec_get_int(blob, dev_of_offset(dev), propname, 0);
if (rate)
pic32_set_refclk(priv, i, pll_hz, rate, ROCLK_SRC_SPLL);
}
fdt_addr_t addr;
fdt_size_t size;
- addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size);
+ addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
+ &size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
goto fail;
}
- if (drv->ofdata_to_platdata && dev->of_offset >= 0) {
+ if (drv->ofdata_to_platdata && dev_of_offset(dev) >= 0) {
ret = drv->ofdata_to_platdata(dev);
if (ret)
goto fail;
*devp = NULL;
list_for_each_entry(dev, &parent->child_head, sibling_node) {
- if (dev->of_offset == of_offset) {
+ if (dev_of_offset(dev) == of_offset) {
*devp = dev;
return 0;
}
{
struct udevice *dev, *found;
- if (parent->of_offset == of_offset)
+ if (dev_of_offset(parent) == of_offset)
return parent;
list_for_each_entry(dev, &parent->child_head, sibling_node) {
int len = 0;
int na, ns;
- na = fdt_address_cells(gd->fdt_blob, dev->parent->of_offset);
+ na = fdt_address_cells(gd->fdt_blob,
+ dev_of_offset(dev->parent));
if (na < 1) {
debug("bad #address-cells\n");
return FDT_ADDR_T_NONE;
}
- ns = fdt_size_cells(gd->fdt_blob, dev->parent->of_offset);
+ ns = fdt_size_cells(gd->fdt_blob, dev_of_offset(dev->parent));
if (ns < 0) {
debug("bad #size-cells\n");
return FDT_ADDR_T_NONE;
}
- reg = fdt_getprop(gd->fdt_blob, dev->of_offset, "reg", &len);
+ reg = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "reg",
+ &len);
if (!reg || (len <= (index * sizeof(fdt32_t) * (na + ns)))) {
debug("Req index out of range\n");
return FDT_ADDR_T_NONE;
* bus setups.
*/
addr = fdt_translate_address((void *)gd->fdt_blob,
- dev->of_offset, reg);
+ dev_of_offset(dev), reg);
} else {
/*
* Use the "simple" translate function for less complex
* bus setups.
*/
addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
- dev->parent->of_offset,
- dev->of_offset, "reg",
- index, NULL, false);
+ dev_of_offset(dev->parent), dev_of_offset(dev),
+ "reg", index, NULL, false);
if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) {
if (device_get_uclass_id(dev->parent) ==
UCLASS_SIMPLE_BUS)
* next call to the exisiting dev_get_xxx function which handles
* all config options.
*/
- fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, dev->of_offset,
+ fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, dev_of_offset(dev),
"reg", index, size, false);
/*
#if CONFIG_IS_ENABLED(OF_CONTROL)
int index;
- index = fdt_stringlist_search(gd->fdt_blob, dev->of_offset,
+ index = fdt_stringlist_search(gd->fdt_blob, dev_of_offset(dev),
"reg-names", name);
if (index < 0)
return index;
{
const void *fdt = gd->fdt_blob;
- return !fdt_node_check_compatible(fdt, dev->of_offset, compat);
+ return !fdt_node_check_compatible(fdt, dev_of_offset(dev), compat);
}
bool of_machine_is_compatible(const char *compat)
int parent;
int len;
- parent = dev->parent->of_offset;
+ parent = dev_of_offset(dev->parent);
addr_len = fdt_address_cells(blob, parent);
size_len = fdt_size_cells(blob, parent);
both_len = addr_len + size_len;
- cell = fdt_getprop(blob, dev->of_offset, "reg", &len);
+ cell = fdt_getprop(blob, dev_of_offset(dev), "reg", &len);
len /= sizeof(*cell);
count = len / both_len;
if (!cell || !count)
int dm_scan_fdt_dev(struct udevice *dev)
{
- if (dev->of_offset == -1)
+ if (dev_of_offset(dev) == -1)
return 0;
- return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset,
+ return dm_scan_fdt_node(dev, gd->fdt_blob, dev_of_offset(dev),
gd->flags & GD_FLG_RELOC ? false : true);
}
u32 cell[3];
int ret;
- ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "ranges",
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), "ranges",
cell, ARRAY_SIZE(cell));
if (!ret) {
struct simple_bus_plat *plat = dev_get_uclass_platdata(dev);
return ret;
list_for_each_entry(dev, &uc->dev_head, uclass_node) {
- if (dev->of_offset == node) {
+ if (dev_of_offset(dev) == node) {
*devp = dev;
return 0;
}
int ret;
*devp = NULL;
- find_phandle = fdtdec_get_int(gd->fdt_blob, parent->of_offset, name,
+ find_phandle = fdtdec_get_int(gd->fdt_blob, dev_of_offset(parent), name,
-1);
if (find_phandle <= 0)
return -ENOENT;
return ret;
list_for_each_entry(dev, &uc->dev_head, uclass_node) {
- uint phandle = fdt_get_phandle(gd->fdt_blob, dev->of_offset);
+ uint phandle;
+
+ phandle = fdt_get_phandle(gd->fdt_blob, dev_of_offset(dev));
if (phandle == find_phandle) {
*devp = dev;
return ret;
/* Parse the data that only we need */
- pdata->default_char = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ pdata->default_char = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"character", '@');
return 0;
int demo_parse_dt(struct udevice *dev)
{
struct dm_demo_pdata *pdata = dev_get_platdata(dev);
- int dn = dev->of_offset;
+ int dn = dev_of_offset(dev);
pdata->sides = fdtdec_get_int(gd->fdt_blob, dn, "sides", 0);
pdata->colour = fdt_getprop(gd->fdt_blob, dn, "colour", NULL);
char *str, name[32];
int ret;
const void *fdt = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
snprintf(name, sizeof(name), "%s_", dev->name);
str = strdup(name);
plat->regs = map_physmem(dev_get_addr(dev),
sizeof(struct altera_pio_regs),
MAP_NOCACHE);
- plat->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ plat->gpio_count = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"altr,gpio-bank-width", 32);
- plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ plat->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
"gpio-bank-name", NULL);
return 0;
static int atmel_pio4_bind(struct udevice *dev)
{
- return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
+ return dm_scan_fdt_node(dev, gd->fdt_blob, dev_of_offset(dev), false);
}
static int atmel_pio4_probe(struct udevice *dev)
pioctrl_data = (struct atmel_pioctrl_data *)dev_get_driver_data(dev);
nbanks = pioctrl_data->nbanks;
- uc_priv->bank_name = fdt_get_name(gd->fdt_blob, dev->of_offset, NULL);
+ uc_priv->bank_name = fdt_get_name(gd->fdt_blob, dev_of_offset(dev),
+ NULL);
uc_priv->gpio_count = nbanks * ATMEL_PIO_NPINS_PER_BANK;
return 0;
if (plat)
return 0;
- base = fdtdec_get_addr(blob, dev->of_offset, "reg");
+ base = fdtdec_get_addr(blob, dev_of_offset(dev), "reg");
if (base == FDT_ADDR_T_NONE) {
debug("Can't get the GPIO register base address\n");
return -ENXIO;
}
- for (node = fdt_first_subnode(blob, dev->of_offset);
+ for (node = fdt_first_subnode(blob, dev_of_offset(dev));
node > 0;
node = fdt_next_subnode(blob, node)) {
if (!fdtdec_get_bool(blob, node, "gpio-controller"))
if (ret)
goto err;
- subdev->of_offset = node;
+ dev_set_of_offset(subdev, node);
bank++;
}
* calls in gpio_request_by_name(), but we can do this until
* gpio_request_by_name_nodev() can be dropped.
*/
- return gpio_request_by_name_nodev(gd->fdt_blob, dev->of_offset,
+ return gpio_request_by_name_nodev(gd->fdt_blob, dev_of_offset(dev),
list_name, index, desc, flags);
}
* calls in gpio_request_by_name(), but we can do this until
* gpio_request_list_by_name_nodev() can be dropped.
*/
- return gpio_request_list_by_name_nodev(gd->fdt_blob, dev->of_offset,
+ return gpio_request_list_by_name_nodev(gd->fdt_blob, dev_of_offset(dev),
list_name, desc, max_count,
flags);
}
{
int ret;
- ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
+ ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev),
list_name, "#gpio-cells", 0, -1,
NULL);
if (ret) {
if (ret)
return ret;
- bank = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1);
+ bank = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1);
if (bank == -1) {
debug("%s: Invalid bank number %d\n", __func__, bank);
return -EINVAL;
}
plat->bank = bank;
plat->base_addr = gpiobase;
- plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ plat->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
"bank-name", NULL);
return 0;
if (ret)
return ret;
- offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1);
+ offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1);
if (offset == -1) {
debug("%s: Invalid register offset %d\n", __func__, offset);
return -EINVAL;
}
plat->offset = offset;
plat->base_addr = gpiobase + offset;
- plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ plat->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
"bank-name", NULL);
return 0;
struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
struct gpio_dev_priv *uc_priv = dev->uclass_priv;
- if (dev->of_offset == -1) {
+ if (dev_of_offset(dev) == -1) {
/* Tell the uclass how many GPIOs we have */
uc_priv->gpio_count = LPC32XX_GPIOS;
}
fdt_addr_t addr;
fdt_size_t size;
- addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, dev->of_offset,
- "reg", 0, &size, false);
+ addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob,
+ dev_of_offset(dev), "reg", 0, &size, false);
plat->addr = addr;
plat->size = size;
- plat->ngpios = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
- "ngpios", 32);
+ plat->ngpios = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "ngpios", 32);
return 0;
}
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"gpio-count", 0);
- uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
"gpio-bank-name", NULL);
if (uc_priv->bank_name == NULL)
uc_priv->bank_name = "soc";
return -ENOMEM;
plat->base = base_addr;
- plat->port_name = fdt_get_name(gd->fdt_blob, dev->of_offset, NULL);
+ plat->port_name = fdt_get_name(gd->fdt_blob, dev_of_offset(dev), NULL);
dev->platdata = plat;
return 0;
return -ENODEV;
}
- addr = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", 0);
+ addr = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", 0);
if (addr == 0)
return -ENODEV;
int n_latch;
- uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"gpio-count", 16);
- uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
"gpio-bank-name", NULL);
if (!uc_priv->bank_name)
uc_priv->bank_name = fdt_get_name(gd->fdt_blob,
- dev->of_offset, NULL);
+ dev_of_offset(dev), NULL);
- n_latch = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ n_latch = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"lines-initial-states", 0);
plat->out = ~n_latch;
char *end;
int bank;
- addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size);
+ addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
+ &size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"gpio-count", 0);
- uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
"gpio-bank-name", NULL);
if (uc_priv->bank_name == NULL)
uc_priv->bank_name = "pm8916";
return 0;
base = (struct s5p_gpio_bank *)dev_get_addr(parent);
- for (node = fdt_first_subnode(blob, parent->of_offset), bank = base;
+ for (node = fdt_first_subnode(blob, dev_of_offset(parent)), bank = base;
node > 0;
node = fdt_next_subnode(blob, node), bank++) {
struct exynos_gpio_platdata *plat;
if (ret)
return ret;
- dev->of_offset = node;
+ dev_set_of_offset(dev, node);
reg = dev_get_addr(dev);
if (reg != FDT_ADDR_T_NONE)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"num-gpios", 0);
- uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
"gpio-bank-name", NULL);
return 0;
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- if (dev->of_offset == -1) {
+ if (dev_of_offset(dev) == -1) {
/* Tell the uclass how many GPIOs we have */
uc_priv->gpio_count = CONFIG_SANDBOX_GPIO_COUNT;
}
plat->bank_name, plat, -1, &dev);
if (ret)
return ret;
- dev->of_offset = parent->of_offset;
+ dev_set_of_offset(dev, dev_of_offset(parent));
}
return 0;
-1, &dev);
if (ret)
return ret;
- dev->of_offset = parent->of_offset;
+ dev_set_of_offset(dev, dev_of_offset(parent));
}
return 0;
* This driver does not make use of interrupts, other than to figure
* out the number of GPIO banks
*/
- if (!fdt_getprop(gd->fdt_blob, parent->of_offset, "interrupts", &len))
+ if (!fdt_getprop(gd->fdt_blob, dev_of_offset(parent), "interrupts",
+ &len))
return -EINVAL;
bank_count = len / 3 / sizeof(u32);
ctlr = (struct gpio_ctlr *)dev_get_addr(parent);
plat->port_name, plat, -1, &dev);
if (ret)
return ret;
- dev->of_offset = parent->of_offset;
+ dev_set_of_offset(dev, dev_of_offset(parent));
}
}
plat->base = base_addr;
plat->chip = dev->req_seq;
- plat->port_name = fdt_get_name(gd->fdt_blob, dev->of_offset, NULL);
+ plat->port_name = fdt_get_name(gd->fdt_blob, dev_of_offset(dev), NULL);
dev->platdata = plat;
return 0;
{
const void *blob = gd->fdt_blob;
struct at91_i2c_bus *bus = dev_get_priv(dev);
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
bus->regs = (struct at91_i2c_regs *)dev_get_addr(dev);
bus->pdata = (struct at91_i2c_pdata *)dev_get_driver_data(dev);
{
struct cros_ec_i2c_bus *i2c_bus = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
i2c_bus->remote_bus = fdtdec_get_uint(blob, node, "google,remote-bus",
0);
struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
int node;
- node = dev->of_offset;
+ node = dev_of_offset(dev);
i2c_bus->hsregs = (struct exynos5_hsi2c *)dev_get_addr(dev);
struct fsl_i2c_dev *dev = dev_get_priv(bus);
fdt_addr_t addr;
fdt_size_t size;
+ int node = dev_of_offset(bus);
- addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, bus->of_offset,
- "reg", 0, &size, false);
+ addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, node, "reg", 0,
+ &size, false);
dev->base = map_sysmem(CONFIG_SYS_IMMR + addr, size);
if (!dev->base)
return -ENOMEM;
- dev->index = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
- "cell-index", -1);
- dev->slaveadd = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+ dev->index = fdtdec_get_int(gd->fdt_blob, node, "cell-index", -1);
+ dev->slaveadd = fdtdec_get_int(gd->fdt_blob, node,
"u-boot,i2c-slave-addr", 0x7f);
- dev->speed = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
- "clock-frequency", 400000);
+ dev->speed = fdtdec_get_int(gd->fdt_blob, node, "clock-frequency",
+ 400000);
dev->i2c_clk = dev->index ? gd->arch.i2c2_clk : gd->arch.i2c1_clk;
{
struct i2c_gpio_bus *bus = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int ret;
ret = gpio_request_list_by_name(dev, "gpios", bus->gpios,
#if CONFIG_IS_ENABLED(OF_CONTROL)
struct dm_i2c_bus *i2c = dev_get_uclass_priv(dev);
- i2c->speed_hz = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ i2c->speed_hz = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"clock-frequency", 100000);
return dm_i2c_set_bus_speed(dev, i2c->speed_hz);
#if CONFIG_IS_ENABLED(OF_CONTROL)
struct dm_i2c_chip *plat = dev_get_parent_platdata(dev);
- if (dev->of_offset == -1)
+ if (dev_of_offset(dev) == -1)
return 0;
- return i2c_chip_ofdata_to_platdata(gd->fdt_blob, dev->of_offset, plat);
+ return i2c_chip_ofdata_to_platdata(gd->fdt_blob, dev_of_offset(dev),
+ plat);
#else
return 0;
#endif
{
struct i2c_arbitrator_priv *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int ret;
debug("%s: %s\n", __func__, dev->name);
struct i2c_mux_bus *plat = dev_get_parent_platdata(dev);
int channel;
- channel = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1);
+ channel = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1);
if (channel < 0)
return -EINVAL;
plat->channel = channel;
* There is no compatible string in the sub-nodes, so we must manually
* bind these
*/
- for (offset = fdt_first_subnode(blob, mux->of_offset);
+ for (offset = fdt_first_subnode(blob, dev_of_offset(mux));
offset > 0;
offset = fdt_next_subnode(blob, offset)) {
struct udevice *dev;
{
struct pca954x_priv *priv = dev_get_priv(dev);
- priv->addr = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", 0);
+ priv->addr = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", 0);
if (!priv->addr) {
debug("MUX not found\n");
return -ENODEV;
if (!dev->base)
return -ENOMEM;
- dev->index = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+ dev->index = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
"cell-index", -1);
- dev->slaveadd = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+ dev->slaveadd = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
"u-boot,i2c-slave-addr", 0x0);
- dev->speed = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+ dev->speed = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
"clock-frequency", 100000);
return 0;
}
{
struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
const void *fdt = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
fdt_addr_t addr;
int ret, ret2;
struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
int node;
- node = dev->of_offset;
+ node = dev_of_offset(dev);
i2c_bus->regs = (struct s3c24x0_i2c *)dev_get_addr(dev);
{
struct tegra186_bpmp_i2c *priv = dev_get_priv(dev);
- priv->bpmp_bus_id = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ priv->bpmp_bus_id = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"nvidia,bpmp-bus-id", U32_MAX);
if (priv->bpmp_bus_id == U32_MAX) {
debug("%s: could not parse nvidia,bpmp-bus-id\n", __func__);
struct stdio_dev *sdev = &uc_priv->sdev;
struct input_config *input = &uc_priv->input;
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int ret;
if (cros_ec_keyb_decode_fdt(blob, node, priv))
struct input_config *input = &uc_priv->input;
int ret;
- if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
+ if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
"intel,duplicate-por"))
priv->quirks |= QUIRK_DUP_POR;
struct keyboard_priv *uc_priv = dev_get_uclass_priv(dev);
struct stdio_dev *sdev = &uc_priv->sdev;
struct input_config *input = &uc_priv->input;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int ret;
priv->kbc = (struct kbc_tegra *)dev_get_addr(dev);
int node;
int ret;
- for (node = fdt_first_subnode(blob, parent->of_offset);
+ for (node = fdt_first_subnode(blob, dev_of_offset(parent));
node > 0;
node = fdt_next_subnode(blob, node)) {
struct led_uclass_plat *uc_plat;
debug("%s(dev=%p, index=%d, chan=%p)\n", __func__, dev, index, chan);
- ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
+ ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev),
"mboxes", "#mbox-cells", 0,
index, &args);
if (ret) {
debug("%s(dev=%p, name=%s, chan=%p)\n", __func__, dev, name, chan);
- index = fdt_stringlist_search(gd->fdt_blob, dev->of_offset,
+ index = fdt_stringlist_search(gd->fdt_blob, dev_of_offset(dev),
"mbox-names", name);
if (index < 0) {
debug("fdt_stringlist_search() failed: %d\n", index);
{
struct cros_ec_dev *cdev = dev_get_uclass_priv(dev);
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
char id[MSG_BYTES];
cdev->dev = dev;
int err;
memcpy(ec, &s_state, sizeof(*ec));
- err = cros_ec_decode_ec_flash(blob, dev->of_offset, &ec->ec_config);
+ err = cros_ec_decode_ec_flash(blob, dev_of_offset(dev), &ec->ec_config);
if (err)
return err;
keyb_dev;
device_find_next_child(&keyb_dev)) {
if (device_get_uclass_id(keyb_dev) == UCLASS_KEYBOARD) {
- node = keyb_dev->of_offset;
+ node = dev_of_offset(keyb_dev);
break;
}
}
{
struct sandbox_i2c_flash_plat_data *plat = dev_get_platdata(dev);
- plat->size = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ plat->size = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"sandbox,size", 32);
- plat->filename = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ plat->filename = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
"sandbox,filename", NULL);
if (!plat->filename) {
debug("%s: No filename for device '%s'\n", __func__,
debug("%s(dev=%p)\n", __func__, dev);
ret = device_bind_driver_to_node(dev, "tegra186_clk", "tegra186_clk",
- dev->of_offset, &child);
+ dev_of_offset(dev), &child);
if (ret)
return ret;
ret = device_bind_driver_to_node(dev, "tegra186_reset",
- "tegra186_reset", dev->of_offset,
+ "tegra186_reset", dev_of_offset(dev),
&child);
if (ret)
return ret;
ret = device_bind_driver_to_node(dev, "tegra186_power_domain",
"tegra186_power_domain",
- dev->of_offset, &child);
+ dev_of_offset(dev), &child);
if (ret)
return ret;
struct fdtdec_phandle_args args;
fdt_addr_t reg;
- ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
+ ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev),
"shmem", NULL, 0, index, &args);
if (ret < 0) {
error("fdtdec_parse_phandle_with_args() failed: %d\n", ret);
debug("%s(dev=%p)\n", __func__, dev);
ret = device_bind_driver_to_node(dev, "tegra_car_clk", "tegra_car_clk",
- dev->of_offset, &child);
+ dev_of_offset(dev), &child);
if (ret)
return ret;
ret = device_bind_driver_to_node(dev, "tegra_car_reset",
- "tegra_car_reset", dev->of_offset,
+ "tegra_car_reset", dev_of_offset(dev),
&child);
if (ret)
return ret;
host->ioaddr = (void *)dev_get_addr(dev);
host->quirks = 0;
- host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"bus-width", 4);
caps = sdhci_readl(host, SDHCI_CAPABILITIES);
struct dwmci_host *host = &priv->host;
int err;
- err = exynos_dwmci_get_config(gd->fdt_blob, dev->of_offset, host);
+ err = exynos_dwmci_get_config(gd->fdt_blob, dev_of_offset(dev), host);
if (err)
return err;
err = do_dwmci_init(host);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
const void *fdt = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
fdt_addr_t addr;
unsigned int val;
int ret;
static int msm_sdc_clk_init(struct udevice *dev)
{
- uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
- "clock-frequency", 400000);
+ int node = dev_of_offset(dev);
+ uint clk_rate = fdtdec_get_uint(gd->fdt_blob, node, "clock-frequency",
+ 400000);
uint clkd[2]; /* clk_id and clk_no */
int clk_offset;
struct udevice *clk_dev;
struct clk clk;
int ret;
- ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clock", clkd,
- 2);
+ ret = fdtdec_get_int_array(gd->fdt_blob, node, "clock", clkd, 2);
if (ret)
return ret;
struct udevice *parent = dev->parent;
struct msm_sdhc *priv = dev_get_priv(dev);
struct sdhci_host *host = &priv->host;
+ int node = dev_of_offset(dev);
host->name = strdup(dev->name);
host->ioaddr = (void *)dev_get_addr(dev);
- host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
- "bus-width", 4);
- host->index = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, "index", 0);
+ host->bus_width = fdtdec_get_int(gd->fdt_blob, node, "bus-width", 4);
+ host->index = fdtdec_get_uint(gd->fdt_blob, node, "index", 0);
priv->base = (void *)fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
- parent->of_offset,
- dev->of_offset,
- "reg", 1, NULL,
- false);
+ dev_of_offset(parent), node, "reg", 1, NULL, false);
if (priv->base == (void *)FDT_ADDR_T_NONE ||
host->ioaddr == (void *)FDT_ADDR_T_NONE)
return -EINVAL;
{
struct omap_hsmmc_data *priv = dev_get_priv(dev);
const void *fdt = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
struct mmc_config *cfg;
int val;
fdt_size_t size;
int ret;
- addr = fdtdec_get_addr_size(fdt, dev->of_offset, "reg", &size);
+ addr = fdtdec_get_addr_size(fdt, dev_of_offset(dev), "reg", &size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
host->ioaddr = ioremap(addr, size);
host->name = dev->name;
host->quirks = SDHCI_QUIRK_NO_HISPD_BIT;
- host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"bus-width", 4);
host->ops = &pic32_sdhci_ops;
- ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
"clock-freq-min-max", f_min_max, 2);
if (ret) {
printf("sdhci: clock-freq-min-max not found\n");
host->name = dev->name;
host->ioaddr = (void *)dev_get_addr(dev);
- host->buswidth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"bus-width", 4);
host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
host->priv = dev;
/* use non-removeable as sdcard and emmc as judgement */
- if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "non-removable"))
+ if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), "non-removable"))
host->dev_index = 0;
else
host->dev_index = 1;
- priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"fifo-depth", 0);
if (priv->fifo_depth < 0)
return -EINVAL;
- priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
+ priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
"fifo-mode");
- if (fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+ if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
"clock-freq-min-max", priv->minmax, 2))
return -EINVAL;
#endif
struct clk clk;
- max_frequency = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ max_frequency = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"max-frequency", 0);
ret = clk_get_by_index(dev, 0, &clk);
if (!ret) {
struct sdhci_host *host = dev_get_priv(dev);
int ret;
- ret = sdhci_get_config(gd->fdt_blob, dev->of_offset, host);
+ ret = sdhci_get_config(gd->fdt_blob, dev_of_offset(dev), host);
if (ret)
return ret;
return -EINVAL;
}
- fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"fifo-depth", 0);
if (fifo_depth < 0) {
printf("DWMMC: Can't get FIFO depth\n");
host->name = dev->name;
host->ioaddr = (void *)dev_get_addr(dev);
- host->buswidth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"bus-width", 4);
host->clksel = socfpga_dwmci_clksel;
host->bus_hz = clk;
host->fifoth_val = MSIZE(0x2) |
RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
- priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"drvsel", 3);
- priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"smplsel", 0);
host->priv = priv;
priv->cfg.name = "Tegra SD/MMC";
priv->cfg.ops = &tegra_mmc_ops;
- bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "bus-width",
- 1);
+ bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "bus-width", 1);
priv->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
priv->cfg.host_caps = 0;
plat->cfg.name = dev->name;
plat->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
- switch (fdtdec_get_int(gd->fdt_blob, dev->of_offset, "bus-width", 1)) {
+ switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
+ 1)) {
case 8:
plat->cfg.host_caps |= MMC_MODE_8BIT;
break;
return -EINVAL;
}
- if (fdt_get_property(gd->fdt_blob, dev->of_offset, "non-removable",
+ if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
NULL))
priv->caps |= UNIPHIER_SD_CAP_NONREMOVABLE;
armada_3700_soc_pad_voltage_set(host);
host->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_DDR_52MHz;
- switch (fdtdec_get_int(gd->fdt_blob, dev->of_offset, "bus-width", 1)) {
+ switch (fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "bus-width",
+ 1)) {
case 8:
host->host_caps |= MMC_MODE_8BIT;
break;
if (of_device_is_compatible(dev, "marvell,armada-3700-sdhci"))
priv->pad_ctrl_reg = (void *)dev_get_addr_index(dev, 1);
- name = fdt_getprop(gd->fdt_blob, dev->of_offset, "marvell,pad-type",
+ name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "marvell,pad-type",
NULL);
if (name) {
if (0 == strncmp(name, "sd", 2)) {
{
struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
void *blob = (void *)gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
const char *list, *end;
const fdt32_t *cell;
void *base;
static int cfi_flash_probe(struct udevice *dev)
{
void *blob = (void *)gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
const fdt32_t *cell;
phys_addr_t addr;
int parent, addrc, sizec;
static int pic32_flash_probe(struct udevice *dev)
{
void *blob = (void *)gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
const char *list, *end;
const fdt32_t *cell;
unsigned long addr, size;
{
struct sandbox_spi_flash_plat_data *pdata = dev_get_platdata(dev);
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
pdata->filename = fdt_getprop(blob, node, "sandbox,filename", NULL);
pdata->device_name = fdt_getprop(blob, node, "compatible", NULL);
debug("%s: busnum=%u, cs=%u: binding SPI flash emulation: ",
__func__, busnum, cs);
ret = sandbox_sf_bind_emul(state, busnum, cs, bus,
- slave->of_offset, slave->name);
+ dev_of_offset(slave), slave->name);
if (ret) {
debug("failed (err=%d)\n", ret);
return ret;
#ifdef CONFIG_DM_SPI_FLASH
fdt_addr_t addr;
fdt_size_t size;
- int node = flash->dev->of_offset;
+ int node = dev_of_offset(flash->dev);
addr = fdtdec_get_addr_size(blob, node, "memory-map", &size);
if (addr == FDT_ADDR_T_NONE) {
{
int offset;
- offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, "phy");
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev), "phy");
if (offset <= 0) {
debug("%s: PHY OF node not found (ret=%i)\n", __func__, offset);
return -EINVAL;
struct eth_pdata *pdata = dev_get_platdata(dev);
struct altera_tse_priv *priv = dev_get_priv(dev);
void *blob = (void *)gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
const char *list, *end;
const fdt32_t *cell;
void *base, *desc_mem = NULL;
const char *phy_mode;
pdata->phy_interface = -1;
- phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
+ NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
int slave, u8 *mac_addr)
{
void *fdt = (void *)gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
u32 macid_lsb;
u32 macid_msb;
fdt32_t gmii = 0;
u8 *mac_addr)
{
void *fdt = (void *)gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
u32 macid_lo;
u32 macid_hi;
fdt32_t gmii = 0;
#ifdef CONFIG_DM_ETH
if (slave->data->phy_of_handle)
- phydev->dev->of_offset = slave->data->phy_of_handle;
+ dev_set_of_offset(phydev->dev, slave->data->phy_of_handle);
#endif
priv->phydev = phydev;
const char *phy_mode;
const char *phy_sel_compat = NULL;
const void *fdt = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int subnode;
int slave_index = 0;
int active_slave;
pdata->iobase = dev_get_addr(dev);
pdata->phy_interface = -1;
- phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
+ NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
}
pdata->max_speed = 0;
- cell = fdt_getprop(gd->fdt_blob, dev->of_offset, "max-speed", NULL);
+ cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
if (cell)
pdata->max_speed = fdt32_to_cpu(*cell);
#ifdef CONFIG_DM_GPIO
- if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
+ if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
"snps,reset-active-low"))
reset_flags |= GPIOD_ACTIVE_LOW;
ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
&priv->reset_gpio, reset_flags);
if (ret == 0) {
- ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
"snps,reset-delays-us", dw_pdata->reset_delays, 3);
} else if (ret == -ENOENT) {
ret = 0;
priv->eth = (struct ethernet_regs *)pdata->iobase;
pdata->phy_interface = -1;
- phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
+ NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
{
struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
- pdata->tx_delay = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ pdata->tx_delay = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"tx-delay", 0x30);
- pdata->rx_delay = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ pdata->rx_delay = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"rx-delay", 0x10);
return designware_eth_ofdata_to_platdata(dev);
struct ks2_eth_priv *priv = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_platdata(dev);
const void *fdt = gd->fdt_blob;
- int slave = dev->of_offset;
+ int slave = dev_of_offset(dev);
int interfaces;
int gbe;
int netcp_devices;
int netcp_devices;
int gbe;
- netcp_devices = fdt_subnode_offset(fdt, dev->of_offset,
+ netcp_devices = fdt_subnode_offset(fdt, dev_of_offset(dev),
"netcp-devices");
gbe = fdt_subnode_offset(fdt, netcp_devices, "gbe");
ks2_eth_bind_slaves(dev, gbe, &gbe_0);
- ks2_eth_parse_slave_interface(dev->of_offset, gbe_0, priv, pdata);
+ ks2_eth_parse_slave_interface(dev_of_offset(dev), gbe_0, priv, pdata);
pdata->iobase = dev_get_addr(dev);
#ifdef CONFIG_DM_ETH
const char *phy_mode;
- phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
+ NULL);
if (phy_mode)
macb->phy_interface = phy_get_interface_by_name(phy_mode);
if (macb->phy_interface == -1) {
struct eth_pdata *pdata = dev_get_platdata(dev);
struct mvneta_port *pp = dev_get_priv(dev);
void *blob = (void *)gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
struct mii_dev *bus;
unsigned long addr;
void *bd_space;
/* Get phy-mode / phy_interface from DT */
pdata->phy_interface = -1;
- phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
+ NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
return err;
}
- return mvpp2_port_probe(dev, port, dev->of_offset, priv,
+ return mvpp2_port_probe(dev, port, dev_of_offset(dev), priv,
&buffer_loc.first_rxq);
}
static int mvpp2_base_bind(struct udevice *parent)
{
const void *blob = gd->fdt_blob;
- int node = parent->of_offset;
+ int node = dev_of_offset(parent);
struct uclass_driver *drv;
struct udevice *dev;
struct eth_pdata *plat;
/* Create child device UCLASS_ETH and bind it */
device_bind(parent, &mvpp2_driver, name, plat, subnode, &dev);
- dev->of_offset = subnode;
+ dev_set_of_offset(dev, subnode);
}
return 0;
return -EOPNOTSUPP;
for (i = 0; i < ofcfg->grpsz; i++) {
- val[i] = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ val[i] = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
ofcfg->grp[i].name, -1);
offset = ofcfg->grp[i].off;
if (val[i] == -1) {
struct dp83867_private *dp83867 = phydev->priv;
struct udevice *dev = phydev->dev;
- dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"ti,rx-internal-delay", -1);
- dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"ti,tx-internal-delay", -1);
- dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"ti,fifo-depth", -1);
return 0;
u32 phytype;
debug("%s\n", __func__);
- phytype = fdtdec_get_int(gd->fdt_blob, phydev->dev->of_offset,
+ phytype = fdtdec_get_int(gd->fdt_blob, dev_of_offset(phydev->dev),
"phy-type", -1);
if (phytype == XAE_PHY_TYPE_1000BASE_X)
phydev->flags |= XAE_PHY_TYPE_1000BASE_X;
int offset = 0;
int phy_addr = -1;
- addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size);
+ addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
+ &size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
/* get phy mode */
pdata->phy_interface = -1;
- phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
+ NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
}
/* get phy addr */
- offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
"phy-handle");
if (offset > 0)
phy_addr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
/* phy reset gpio */
- gpio_request_by_name_nodev(gd->fdt_blob, dev->of_offset,
+ gpio_request_by_name_nodev(gd->fdt_blob, dev_of_offset(dev),
"reset-gpios", 0,
&priv->rst_gpio, GPIOD_IS_OUT);
debug("eth_sandbox_raw: Start\n");
- interface = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ interface = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
"host-raw-interface", NULL);
if (interface == NULL)
return -EINVAL;
debug("eth_sandbox: Start\n");
- fdtdec_get_byte_array(gd->fdt_blob, dev->of_offset, "fake-host-hwaddr",
- priv->fake_host_hwaddr, ARP_HLEN);
+ fdtdec_get_byte_array(gd->fdt_blob, dev_of_offset(dev),
+ "fake-host-hwaddr", priv->fake_host_hwaddr,
+ ARP_HLEN);
priv->recv_packet_buffer = net_rx_packets[0];
return 0;
}
const char *pin_name;
int drive, pull, i;
- offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
"pinctrl-0");
if (offset < 0) {
printf("WARNING: emac: cannot find pinctrl-0 node\n");
struct eth_pdata *pdata = dev_get_platdata(dev);
struct emac_eth_dev *priv = dev_get_priv(dev);
const char *phy_mode;
+ int node = dev_of_offset(dev);
int offset = 0;
pdata->iobase = dev_get_addr_name(dev, "emac");
priv->phyaddr = -1;
priv->use_internal_phy = false;
- offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
"phy");
if (offset > 0)
priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg",
-1);
- phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
}
if (priv->variant == H3_EMAC) {
- if (fdt_getprop(gd->fdt_blob, dev->of_offset,
+ if (fdt_getprop(gd->fdt_blob, node,
"allwinner,use-internal-phy", NULL))
priv->use_internal_phy = true;
}
pdata->iobase = (phys_addr_t)dev_get_addr(dev);
priv->regs = (struct tsec *)pdata->iobase;
- offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
"phy-handle");
if (offset > 0) {
reg = fdtdec_get_int(gd->fdt_blob, offset, "reg", 0);
return -ENOENT;
}
- offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
"tbi-handle");
if (offset > 0) {
reg = fdtdec_get_int(gd->fdt_blob, offset, "reg",
priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
}
- phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
"phy-connection-type", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct axidma_priv *priv = dev_get_priv(dev);
+ int node = dev_of_offset(dev);
int offset = 0;
const char *phy_mode;
pdata->iobase = (phys_addr_t)dev_get_addr(dev);
priv->iobase = (struct axi_regs *)pdata->iobase;
- offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
"axistream-connected");
if (offset <= 0) {
printf("%s: axistream is not found\n", __func__);
priv->phyaddr = -1;
- offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
- "phy-handle");
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
if (offset > 0)
priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
- phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
emaclite->phyaddr = -1;
- offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
"phy-handle");
if (offset > 0)
emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
"reg", -1);
- emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"xlnx,tx-ping-pong", 0);
- emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"xlnx,rx-ping-pong", 0);
printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
priv->phydev->advertising = priv->phydev->supported;
if (priv->phy_of_handle > 0)
- priv->phydev->dev->of_offset = priv->phy_of_handle;
+ dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle);
return phy_config(priv->phydev);
}
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct zynq_gem_priv *priv = dev_get_priv(dev);
+ int node = dev_of_offset(dev);
const char *phy_mode;
pdata->iobase = (phys_addr_t)dev_get_addr(dev);
priv->emio = 0;
priv->phyaddr = -1;
- priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob,
- dev->of_offset, "phy-handle");
+ priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node,
+ "phy-handle");
if (priv->phy_of_handle > 0)
priv->phyaddr = fdtdec_get_int(gd->fdt_blob,
priv->phy_of_handle, "reg", -1);
- phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
+ phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
}
priv->interface = pdata->phy_interface;
- priv->emio = fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "xlnx,emio");
+ priv->emio = fdtdec_get_bool(gd->fdt_blob, node, "xlnx,emio");
printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
priv->phyaddr, phy_string_for_interface(priv->interface));
/* For bridges, use the top-level PCI controller */
if (!device_is_on_pci_bus(bus)) {
hose->ctlr = bus;
- ret = decode_regions(hose, gd->fdt_blob, bus->parent->of_offset,
- bus->of_offset);
+ ret = decode_regions(hose, gd->fdt_blob,
+ dev_of_offset(bus->parent),
+ dev_of_offset(bus));
if (ret) {
debug("%s: Cannot decode regions\n", __func__);
return ret;
struct fdt_pci_addr addr;
int ret;
- if (dev->of_offset == -1)
+ if (dev_of_offset(dev) == -1)
return 0;
/*
* just check the address.
*/
pplat = dev_get_parent_platdata(dev);
- ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset,
+ ret = fdtdec_get_pci_addr(gd->fdt_blob, dev_of_offset(dev),
FDT_PCI_SPACE_CONFIG, "reg", &addr);
if (ret) {
INIT_LIST_HEAD(&pcie->ports);
- if (tegra_pcie_parse_dt(gd->fdt_blob, dev->of_offset, id, pcie))
+ if (tegra_pcie_parse_dt(gd->fdt_blob, dev_of_offset(dev), id, pcie))
return -EINVAL;
return 0;
{
struct ls_pcie *pcie = dev_get_priv(dev);
const void *fdt = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
u8 header_type;
u16 link_sta;
bool ep_mode;
DECLARE_GLOBAL_DATA_PTR;
int err;
- err = fdt_get_resource(gd->fdt_blob, dev->of_offset, "reg",
+ err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",
0, ®_res);
if (err < 0) {
error("\"reg\" resource not found\n");
static int comphy_probe(struct udevice *dev)
{
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
struct chip_serdes_phy_config *chip_cfg = dev_get_priv(dev);
struct comphy_map comphy_map_data[MAX_LANE_OPTIONS];
int subnode;
u32 cell[2];
int ret;
- ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
"interrupts", cell, ARRAY_SIZE(cell));
if (ret < 0)
return -EINVAL;
u32 cell[2];
int ret;
- ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
"interrupts", cell, ARRAY_SIZE(cell));
if (ret < 0)
return -EINVAL;
int exynos_pinctrl_set_state(struct udevice *dev, struct udevice *config)
{
const void *fdt = gd->fdt_blob;
- int node = config->of_offset;
+ int node = dev_of_offset(config);
unsigned int count, idx, pin_num;
unsigned int pinfunc, pinpud, pindrv;
unsigned long reg, value;
int node, gpio = -1, len;
int na, ns;
- na = fdt_address_cells(gd->fdt_blob, dev->parent->of_offset);
+ na = fdt_address_cells(gd->fdt_blob, dev_of_offset(dev->parent));
if (na < 1) {
debug("bad #address-cells\n");
return -EINVAL;
}
- ns = fdt_size_cells(gd->fdt_blob, dev->parent->of_offset);
+ ns = fdt_size_cells(gd->fdt_blob, dev_of_offset(dev->parent));
if (ns < 1) {
debug("bad #size-cells\n");
return -EINVAL;
}
- fdt_for_each_subnode(node, gd->fdt_blob, dev->of_offset) {
+ fdt_for_each_subnode(node, gd->fdt_blob, dev_of_offset(dev)) {
if (fdt_getprop(gd->fdt_blob, node, "gpio-controller", &len)) {
gpio = node;
break;
int mvebu_pinctrl_set_state(struct udevice *dev, struct udevice *config)
{
const void *blob = gd->fdt_blob;
- int node = config->of_offset;
+ int node = dev_of_offset(config);
struct mvebu_pinctrl_priv *priv;
u32 pin_arr[MVEBU_MAX_PINS_PER_BANK];
u32 function;
struct udevice *config)
{
const void *blob = gd->fdt_blob;
- int node = config->of_offset;
+ int node = dev_of_offset(config);
struct mvebu_pinctrl_priv *priv;
u32 func_arr[MVEBU_MAX_PINS_PER_BANK];
int pin, err;
int mvebu_pinctl_probe(struct udevice *dev)
{
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
struct mvebu_pinctrl_priv *priv;
priv = dev_get_priv(dev);
{
struct imx_pinctrl_priv *priv = dev_get_priv(dev);
struct imx_pinctrl_soc_info *info = priv->info;
- int node = config->of_offset;
+ int node = dev_of_offset(config);
const struct fdt_property *prop;
u32 *pin_data;
int npins, size, pin_size;
struct imx_pinctrl_soc_info *info)
{
struct imx_pinctrl_priv *priv = dev_get_priv(dev);
- int node = dev->of_offset, ret;
+ int node = dev_of_offset(dev), ret;
struct fdtdec_phandle_args arg;
fdt_addr_t addr;
fdt_size_t size;
priv->dev = dev;
priv->info = info;
- addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size);
+ addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
+ &size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
{
struct atmel_pio4_port *bank_base;
const void *blob = gd->fdt_blob;
- int node = config->of_offset;
+ int node = dev_of_offset(config);
u32 offset, func, bank, line;
u32 cells[MAX_PINMUX_ENTRIES];
u32 i, conf;
bool is_group, unsigned selector)
{
const void *fdt = gd->fdt_blob;
- int node_offset = config->of_offset;
+ int node_offset = dev_of_offset(config);
const char *propname;
const void *value;
int prop_offset, len, func_selector, param, ret;
struct udevice *config)
{
const void *fdt = gd->fdt_blob;
- int node = config->of_offset;
+ int node = dev_of_offset(config);
const char *subnode_target_type = "pins";
bool is_group = false;
const char *name;
static int pinctrl_select_state_full(struct udevice *dev, const char *statename)
{
const void *fdt = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
char propname[32]; /* long enough */
const fdt32_t *list;
uint32_t phandle;
static int pinconfig_post_bind(struct udevice *dev)
{
const void *fdt = gd->fdt_blob;
- int offset = dev->of_offset;
+ int offset = dev_of_offset(dev);
bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC);
const char *name;
int ret;
int ret;
u32 cell[2];
- ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
"interrupts", cell, ARRAY_SIZE(cell));
if (ret < 0)
return -EINVAL;
struct pic32_pinctrl_priv *priv = dev_get_priv(dev);
struct fdt_resource res;
void *fdt = (void *)gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int ret;
ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
u32 cell[3];
int ret;
- ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
"interrupts", cell, ARRAY_SIZE(cell));
if (ret < 0)
return -EINVAL;
u32 cell[3];
int ret;
- ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
"interrupts", cell, ARRAY_SIZE(cell));
if (ret < 0)
return -EINVAL;
u32 cell[60], *ptr;
debug("%s: %s %s\n", __func__, dev->name, config->name);
- ret = fdtdec_get_int_array_count(blob, config->of_offset,
+ ret = fdtdec_get_int_array_count(blob, dev_of_offset(config),
"rockchip,pins", cell,
ARRAY_SIZE(cell));
if (ret < 0) {
u32 cell[3];
int ret;
- ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset,
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
"interrupts", cell, ARRAY_SIZE(cell));
if (ret < 0)
return -EINVAL;
debug("%s(dev=%p, power_domain=%p)\n", __func__, dev, power_domain);
- ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
+ ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev),
"power-domains",
"#power-domain-cells", 0, 0,
&args);
int regulators_node;
int children;
- regulators_node = fdt_subnode_offset(blob, dev->of_offset,
+ regulators_node = fdt_subnode_offset(blob, dev_of_offset(dev),
"regulators");
if (regulators_node <= 0) {
debug("%s: %s regulators subnode not found!", __func__,
debug("%s:%d Setting PMIC default registers\n", __func__, __LINE__);
- reg_defaults = fdtdec_locate_byte_array(gd->fdt_blob, emul->of_offset,
- "reg-defaults",
- SANDBOX_PMIC_REG_COUNT);
+ reg_defaults = fdtdec_locate_byte_array(gd->fdt_blob,
+ dev_of_offset(emul), "reg-defaults",
+ SANDBOX_PMIC_REG_COUNT);
if (!reg_defaults) {
error("Property \"reg-defaults\" not found for device: %s!",
int regulators_node;
const void *blob = gd->fdt_blob;
int children;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
regulators_node = fdt_subnode_offset(blob, node, "regulators");
const void *blob = gd->fdt_blob;
int children;
- regulators_node = fdt_subnode_offset(blob, dev->of_offset,
+ regulators_node = fdt_subnode_offset(blob, dev_of_offset(dev),
"voltage-regulators");
if (regulators_node <= 0) {
debug("%s: %s regulators subnode not found!", __func__,
int pmic_node = -1, regulators_node;
const void *blob = gd->fdt_blob;
int children;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int subnode, len;
fdt_for_each_subnode(subnode, blob, node) {
int regulators_node;
const void *blob = gd->fdt_blob;
- regulators_node = fdt_subnode_offset(blob, dev->of_offset,
+ regulators_node = fdt_subnode_offset(blob, dev_of_offset(dev),
"regulators");
if (regulators_node <= 0) {
debug("%s: %s regulators subnode not found!", __func__,
int ret;
debug("%s for '%s' at node offset: %d\n", __func__, pmic->name,
- pmic->of_offset);
+ dev_of_offset(pmic));
for (node = fdt_first_subnode(blob, offset);
node > 0;
int regulators_node;
int children;
- regulators_node = fdt_subnode_offset(blob, dev->of_offset,
+ regulators_node = fdt_subnode_offset(blob, dev_of_offset(dev),
"regulators");
if (regulators_node <= 0) {
debug("%s: %s regulators subnode not found!", __func__,
const void *blob = gd->fdt_blob;
int children;
- node = fdt_subnode_offset(blob, dev->of_offset, "regulators");
+ node = fdt_subnode_offset(blob, dev_of_offset(dev), "regulators");
if (node <= 0) {
debug("%s: %s regulators subnode not found!", __func__,
dev->name);
static int sandbox_pmic_bind(struct udevice *dev)
{
- if (!pmic_bind_children(dev, dev->of_offset, pmic_children_info))
+ if (!pmic_bind_children(dev, dev_of_offset(dev), pmic_children_info))
error("%s:%d PMIC: %s - no child found!", __func__, __LINE__,
dev->name);
const void *blob = gd->fdt_blob;
int children;
- regulators_node = fdt_subnode_offset(blob, dev->of_offset,
+ regulators_node = fdt_subnode_offset(blob, dev_of_offset(dev),
"regulators");
if (regulators_node <= 0) {
debug("%s: %s regulators subnode not found!", __func__,
struct fixed_regulator_platdata *dev_pdata;
struct gpio_desc *gpio;
const void *blob = gd->fdt_blob;
- int node = dev->of_offset, flags = GPIOD_IS_OUT;
+ int node = dev_of_offset(dev), flags = GPIOD_IS_OUT;
int ret;
dev_pdata = dev_get_platdata(dev);
/* Get optional ramp up delay */
dev_pdata->startup_delay_us = fdtdec_get_uint(gd->fdt_blob,
- dev->of_offset,
+ dev_of_offset(dev),
"startup-delay-us", 0);
return 0;
struct gpio_regulator_platdata *dev_pdata;
struct gpio_desc *gpio;
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int ret, count, i, j;
u32 states_array[8];
struct pwm_regulator_info *priv = dev_get_priv(dev);
struct fdtdec_phandle_args args;
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int ret;
ret = fdtdec_parse_phandle_with_args(blob, node, "pwms", "#pwm-cells",
static int regulator_post_bind(struct udevice *dev)
{
struct dm_regulator_uclass_platdata *uc_pdata;
- int offset = dev->of_offset;
+ int offset = dev_of_offset(dev);
const void *blob = gd->fdt_blob;
const char *property = "regulator-name";
static int regulator_pre_probe(struct udevice *dev)
{
struct dm_regulator_uclass_platdata *uc_pdata;
- int offset = dev->of_offset;
+ int offset = dev_of_offset(dev);
uc_pdata = dev_get_uclass_platdata(dev);
if (!uc_pdata)
if (!dev->platdata) {
#if CONFIG_IS_ENABLED(OF_CONTROL)
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
const void *blob = gd->fdt_blob;
bool tmp;
if (!blob) {
static int ti_of_to_priv(struct udevice *dev,
struct ti_powerproc_privdata *priv)
{
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
const void *blob = gd->fdt_blob;
int tmp;
debug("%s(dev=%p, index=%d, reset_ctl=%p)\n", __func__, dev, index,
reset_ctl);
- ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset,
+ ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev_of_offset(dev),
"resets", "#reset-cells", 0,
index, &args);
if (ret) {
debug("%s(dev=%p, name=%s, reset_ctl=%p)\n", __func__, dev, name,
reset_ctl);
- index = fdt_stringlist_search(gd->fdt_blob, dev->of_offset,
+ index = fdt_stringlist_search(gd->fdt_blob, dev_of_offset(dev),
"reset-names", name);
if (index < 0) {
debug("fdt_stringlist_search() failed: %d\n", index);
plat->regs = map_physmem(dev_get_addr(dev),
sizeof(struct altera_uart_regs),
MAP_NOCACHE);
- plat->uartclk = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ plat->uartclk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"clock-frequency", 0);
return 0;
int ret;
/* we prefer to use a memory-mapped register */
- ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset,
+ ret = fdtdec_get_pci_addr(gd->fdt_blob, dev_of_offset(dev),
FDT_PCI_SPACE_MEM32, "reg",
&pci_addr);
if (ret) {
/* try if there is any i/o-mapped register */
ret = fdtdec_get_pci_addr(gd->fdt_blob,
- dev->of_offset,
+ dev_of_offset(dev),
FDT_PCI_SPACE_IO,
"reg", &pci_addr);
if (ret)
plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE);
#endif
- plat->reg_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ plat->reg_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"reg-offset", 0);
- plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"reg-shift", 0);
err = clk_get_by_index(dev, 0, &clk);
}
if (!plat->clock)
- plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ plat->clock = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"clock-frequency",
CONFIG_SYS_NS16550_CLK);
if (!plat->clock) {
int i;
plat->colour = -1;
- colour = fdt_getprop(gd->fdt_blob, dev->of_offset,
+ colour = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
"sandbox,text-colour", NULL);
if (colour) {
for (i = 0; i < ARRAY_SIZE(ansi_colour); i++) {
DECLARE_GLOBAL_DATA_PTR;
plat->reg = (struct arc_serial_regs *)dev_get_addr(dev);
- plat->uartclk = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ plat->uartclk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"clock-frequency", 0);
return 0;
return -EINVAL;
plat->base = addr;
- plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "clock", 1);
- plat->skip_init = fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
+ plat->clock = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "clock",
+ 1);
+ plat->skip_init = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
"skip-init");
plat->disabled = false;
return 0;
static int msm_uart_clk_init(struct udevice *dev)
{
- uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
+ uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"clock-frequency", 115200);
uint clkd[2]; /* clk_id and clk_no */
int clk_offset;
struct clk clk;
int ret;
- ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clock", clkd,
- 2);
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), "clock",
+ clkd, 2);
if (ret)
return ret;
plat->reg = (struct mxc_uart *)addr;
- plat->use_dte = fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
+ plat->use_dte = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
"fsl,dte-mode");
return 0;
}
int ret;
/* get address */
- addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size);
+ addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
+ &size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
return -EINVAL;
plat->base = addr;
- plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "clock", 1);
+ plat->clock = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "clock",
+ 1);
plat->type = dev_get_driver_data(dev);
- plat->skip_init = fdtdec_get_bool(gd->fdt_blob, dev->of_offset,
+ plat->skip_init = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
"skip-init");
return 0;
}
return -EINVAL;
plat->reg = (struct s5p_uart *)addr;
- plat->port_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ plat->port_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"id", dev->seq);
return 0;
}
struct sh_serial_platdata *plat = dev_get_platdata(dev);
fdt_addr_t addr;
- addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
+ addr = fdtdec_get_addr(gd->fdt_blob, dev_of_offset(dev), "reg");
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
plat->base = addr;
- plat->clk = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "clock", 1);
+ plat->clk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "clock",
+ 1);
plat->type = dev_get_driver_data(dev);
return 0;
}
priv->membase = port;
- priv->uartclk = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ priv->uartclk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"clock-frequency", 0);
tmp = readl(&port->lcr_mcr);
{
struct cadence_spi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
int subnode;
u32 data[4];
int ret;
{
struct davinci_spi_slave *ds = dev_get_priv(bus);
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
ds->regs = dev_map_physmem(bus, sizeof(struct davinci_spi_regs));
if (!ds->regs) {
{
struct dw_spi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
plat->regs = (struct dw_spi *)dev_get_addr(bus);
{
struct exynos_spi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
plat->regs = (struct exynos_spi *)dev_get_addr(bus);
plat->periph_id = pinmux_decode_periph_id(blob, node);
fdt_addr_t addr;
struct fsl_dspi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
if (fdtdec_get_bool(blob, node, "big-endian"))
plat->flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG;
struct fdt_resource res_regs, res_mem;
struct fsl_qspi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
int ret, flash_num = 0, subnode;
if (fdtdec_get_bool(blob, node, "big-endian"))
static int ich_spi_ofdata_to_platdata(struct udevice *dev)
{
struct ich_spi_platdata *plat = dev_get_platdata(dev);
+ int node = dev_of_offset(dev);
int ret;
- ret = fdt_node_check_compatible(gd->fdt_blob, dev->of_offset,
- "intel,ich7-spi");
+ ret = fdt_node_check_compatible(gd->fdt_blob, node, "intel,ich7-spi");
if (ret == 0) {
plat->ich_version = ICHV_7;
} else {
- ret = fdt_node_check_compatible(gd->fdt_blob, dev->of_offset,
+ ret = fdt_node_check_compatible(gd->fdt_blob, node,
"intel,ich9-spi");
if (ret == 0)
plat->ich_version = ICHV_9;
* it should be used to read the input clock and the DT property
* can be removed.
*/
- plat->clock = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+ plat->clock = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
"clock-frequency", 160000);
- plat->frequency = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+ plat->frequency = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
"spi-max-frequency", 40000);
return 0;
{
struct omap3_spi_priv *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
struct omap2_mcspi_platform_config* data =
(struct omap2_mcspi_platform_config*)dev_get_driver_data(dev);
{
struct pic32_spi_priv *priv = dev_get_priv(bus);
struct dm_spi_bus *dm_spi = dev_get_uclass_priv(bus);
+ int node = dev_of_offset(bus);
struct udevice *clkdev;
fdt_addr_t addr;
fdt_size_t size;
int ret;
debug("%s: %d, bus: %i\n", __func__, __LINE__, bus->seq);
- addr = fdtdec_get_addr_size(gd->fdt_blob, bus->of_offset, "reg", &size);
+ addr = fdtdec_get_addr_size(gd->fdt_blob, node, "reg", &size);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
if (!priv->regs)
return -EINVAL;
- dm_spi->max_hz = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
- "spi-max-frequency", 250000000);
+ dm_spi->max_hz = fdtdec_get_int(gd->fdt_blob, node, "spi-max-frequency",
+ 250000000);
/* get clock rate */
ret = clk_get_by_index(bus, 0, &clkdev);
if (ret < 0) {
* of the ongoing transfer. To avoid this sort of error we will drive
* /CS manually by toggling cs-gpio pins.
*/
- ret = gpio_request_by_name_nodev(gd->fdt_blob, bus->of_offset,
- "cs-gpios", 0,
+ ret = gpio_request_by_name_nodev(gd->fdt_blob, node, "cs-gpios", 0,
&priv->cs_gpio, GPIOD_IS_OUT);
if (ret) {
printf("pic32-spi: error, cs-gpios not found\n");
struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
struct rockchip_spi_priv *priv = dev_get_priv(bus);
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
int ret;
plat->base = dev_get_addr(bus);
{
struct soft_spi_platdata *plat = dev->platdata;
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
plat->spi_delay_us = fdtdec_get_int(blob, node, "spi-delay-us", 0);
{
struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
- if (dev->of_offset == -1)
+ if (dev_of_offset(dev) == -1)
return 0;
- return spi_slave_ofdata_to_platdata(gd->fdt_blob, dev->of_offset, plat);
+ return spi_slave_ofdata_to_platdata(gd->fdt_blob, dev_of_offset(dev),
+ plat);
}
#endif
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct dm_spi_bus *spi = dev_get_uclass_priv(bus);
- spi->max_hz = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
+ spi->max_hz = fdtdec_get_int(gd->fdt_blob, dev_of_offset(bus),
"spi-max-frequency", 0);
#endif
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
struct fdt_resource res_regs, res_mem;
struct stm32_qspi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
int ret;
ret = fdt_get_named_resource(blob, node, "reg", "reg-names",
{
struct tegra_spi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
plat->base = dev_get_addr(bus);
plat->periph_id = clock_decode_periph_id(blob, node);
{
struct tegra_spi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
plat->base = dev_get_addr(bus);
plat->periph_id = clock_decode_periph_id(blob, node);
{
struct tegra_spi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
plat->base = dev_get_addr(bus);
plat->periph_id = clock_decode_periph_id(blob, node);
{
struct tegra_spi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
plat->base = dev_get_addr(bus);
plat->periph_id = clock_decode_periph_id(blob, node);
{
struct ti_qspi_priv *priv = dev_get_priv(bus);
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
fdt_addr_t addr;
void *mmap;
{
struct zynq_qspi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
node, "reg");
{
struct zynq_spi_platdata *plat = bus->platdata;
const void *blob = gd->fdt_blob;
- int node = bus->of_offset;
+ int node = dev_of_offset(bus);
plat->regs = (struct zynq_spi_regs *)dev_get_addr(bus);
{
struct udevice *parent = dev->parent;
struct msm_spmi_priv *priv = dev_get_priv(dev);
+ int node = dev_of_offset(dev);
int i;
priv->arb_chnl = dev_get_addr(dev);
priv->spmi_core = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
- parent->of_offset,
- dev->of_offset,
- "reg", 1, NULL,
- false);
+ dev_of_offset(parent), node, "reg", 1, NULL, false);
priv->spmi_obs = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
- parent->of_offset,
- dev->of_offset, "reg",
- 2, NULL, false);
+ dev_of_offset(parent), node, "reg", 2, NULL, false);
if (priv->arb_chnl == FDT_ADDR_T_NONE ||
priv->spmi_core == FDT_ADDR_T_NONE ||
priv->spmi_obs == FDT_ADDR_T_NONE)
* (see the U_BOOT_DEVICE() declaration below) should not do anything.
* If we are that device, return an error.
*/
- if (state->fdt_fname && dev->of_offset == -1)
+ if (state->fdt_fname && dev_of_offset(dev) == -1)
return -ENODEV;
switch (type) {
uc_priv->clock_rate = ret;
} else
uc_priv->clock_rate = fdtdec_get_int(gd->fdt_blob,
- dev->of_offset, "clock-frequency", 0);
+ dev_of_offset(dev), "clock-frequency", 0);
return 0;
}
struct sandbox_flash_plat *plat = dev_get_platdata(dev);
const void *blob = gd->fdt_blob;
- plat->pathname = fdt_getprop(blob, dev->of_offset, "sandbox,filepath",
- NULL);
+ plat->pathname = fdt_getprop(blob, dev_of_offset(dev),
+ "sandbox,filepath", NULL);
return 0;
}
{
struct sandbox_hub_platdata *plat = dev_get_parent_platdata(dev);
- plat->port = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1);
+ plat->port = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg",
+ -1);
return 0;
}
return -EINVAL;
priv->regs = (struct dwc2_core_regs *)addr;
- prop = fdt_getprop(gd->fdt_blob, dev->of_offset, "disable-over-current",
- NULL);
+ prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
+ "disable-over-current", NULL);
if (prop)
priv->oc_disable = true;
}
depth = 0;
- node = fdtdec_next_compatible_subnode(blob, dev->of_offset,
+ node = fdtdec_next_compatible_subnode(blob, dev_of_offset(dev),
COMPAT_SAMSUNG_EXYNOS_USB_PHY, &depth);
if (node <= 0) {
debug("XHCI: Can't get device node for usb3-phy controller\n");
struct ehci_fsl_priv *priv = dev_get_priv(dev);
const void *prop;
- prop = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy_type",
+ prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy_type",
NULL);
if (prop) {
priv->phy_type = (char *)prop;
void *__iomem addr = (void *__iomem)dev_get_addr(dev);
void *__iomem phy_ctrl, *__iomem phy_status;
const void *blob = gd->fdt_blob;
- int offset = dev->of_offset, phy_off;
+ int offset = dev_of_offset(dev), phy_off;
u32 val;
/*
struct usb_platdata *plat = dev_get_platdata(dev);
const char *mode;
- mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "dr_mode", NULL);
+ mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "dr_mode", NULL);
if (mode) {
if (strcmp(mode, "peripheral") == 0)
plat->init_type = USB_INIT_DEVICE;
static int fdt_decode_usb(struct udevice *dev, struct fdt_usb *config)
{
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
const char *phy, *mode;
config->reg = (struct usb_ctlr *)dev_get_addr(dev);
{
struct ehci_vf_priv_data *priv = dev_get_priv(dev);
const void *dt_blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
const char *mode;
priv->portnr = dev->seq;
const void *blob = gd->fdt_blob;
int val;
- if (dev->of_offset == -1)
+ if (dev_of_offset(dev) == -1)
return 0;
/* We only support matching a few things */
- val = fdtdec_get_int(blob, dev->of_offset, "usb,device-class", -1);
+ val = fdtdec_get_int(blob, dev_of_offset(dev), "usb,device-class", -1);
if (val != -1) {
plat->id.match_flags |= USB_DEVICE_ID_MATCH_DEV_CLASS;
plat->id.bDeviceClass = val;
}
- val = fdtdec_get_int(blob, dev->of_offset, "usb,interface-class", -1);
+ val = fdtdec_get_int(blob, dev_of_offset(dev), "usb,interface-class",
+ -1);
if (val != -1) {
plat->id.match_flags |= USB_DEVICE_ID_MATCH_INT_CLASS;
plat->id.bInterfaceClass = val;
}
depth = 0;
- node = fdtdec_next_compatible_subnode(blob, dev->of_offset,
+ node = fdtdec_next_compatible_subnode(blob, dev_of_offset(dev),
COMPAT_SAMSUNG_EXYNOS5_USB3_PHY, &depth);
if (node <= 0) {
debug("XHCI: Can't get device node for usb3-phy controller\n");
/* Set dwc3 usb2 phy config */
reg = readl(&dwc3_reg->g_usb2phycfg[0]);
- if (fdtdec_get_bool(blob, dev->of_offset,
+ if (fdtdec_get_bool(blob, dev_of_offset(dev),
"snps,dis-enblslpm-quirk"))
reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
- utmi_bits = fdtdec_get_int(blob, dev->of_offset,
+ utmi_bits = fdtdec_get_int(blob, dev_of_offset(dev),
"snps,phyif-utmi-bits", -1);
if (utmi_bits == 16) {
reg |= DWC3_GUSB2PHYCFG_PHYIF;
reg |= DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT;
}
- if (fdtdec_get_bool(blob, dev->of_offset,
+ if (fdtdec_get_bool(blob, dev_of_offset(dev),
"snps,dis-u2-freeclk-exists-quirk"))
reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
- if (fdtdec_get_bool(blob, dev->of_offset,
+ if (fdtdec_get_bool(blob, dev_of_offset(dev),
"snps,dis-u2-susphy-quirk"))
reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
struct musb_host_data *mdata = &pdata->mdata;
struct fdt_resource mc, glue;
void *fdt = (void *)gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
void __iomem *mregs;
int ret;
{
struct ti_musb_platdata *platdata = dev_get_platdata(dev);
const void *fdt = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int phys;
int ctrl_mod;
int usb_index;
{
struct ti_musb_platdata *platdata = dev_get_platdata(dev);
const void *fdt = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int ret;
ret = ti_musb_ofdata_to_platdata(dev);
int node;
int ret;
- for (node = fdt_first_subnode(fdt, parent->of_offset); node > 0;
+ for (node = fdt_first_subnode(fdt, dev_of_offset(parent)); node > 0;
node = fdt_next_subnode(fdt, node)) {
struct udevice *dev;
const char *name = fdt_get_name(fdt, node, NULL);
struct display_timing *timing = &priv->timing;
const void *blob = gd->fdt_blob;
- if (fdtdec_decode_display_timing(blob, dev->of_offset,
+ if (fdtdec_decode_display_timing(blob, dev_of_offset(dev),
plat->timing_index, timing)) {
debug("%s: Failed to decode display timing\n", __func__);
return -EINVAL;
if (ret)
return ret;
- params = fdt_getprop(gd->fdt_blob, dev->of_offset, "parade,regs", &len);
+ params = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "parade,regs",
+ &len);
if (!params || len % 3) {
debug("%s: missing/invalid params=%p, len=%x\n", __func__,
params, len);
{
struct broadwell_igd_plat *plat = dev_get_platdata(dev);
struct broadwell_igd_priv *priv = dev_get_priv(dev);
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
const void *blob = gd->fdt_blob;
if (fdtdec_get_int_array(blob, node, "intel,dp-hotplug",
{
struct exynos_dp_priv *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
- unsigned int node = dev->of_offset;
+ unsigned int node = dev_of_offset(dev);
fdt_addr_t addr;
addr = dev_get_addr(dev);
unsigned int offset;
unsigned int node;
- node = dev->of_offset;
+ node = dev_of_offset(dev);
if (fdtdec_get_bool(gd->fdt_blob, node, "samsung,disable-sysmmu"))
exynos_fimd_disable_sysmmu();
int exynos_fb_ofdata_to_platdata(struct udevice *dev)
{
struct exynos_fb_priv *priv = dev_get_priv(dev);
- unsigned int node = dev->of_offset;
+ unsigned int node = dev_of_offset(dev);
const void *blob = gd->fdt_blob;
fdt_addr_t addr;
static int gma_pm_init_post_vbios(struct udevice *dev, int rev, void *gtt_bar)
{
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
u32 reg32, cycle_delay;
debug("GT Power Management Init (post VBIOS)\n");
struct pwm_backlight_priv *priv = dev_get_priv(dev);
struct fdtdec_phandle_args args;
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int index, ret, count, len;
const u32 *cell;
int rk_lvds_read_timing(struct udevice *dev, struct display_timing *timing)
{
if (fdtdec_decode_display_timing
- (gd->fdt_blob, dev->of_offset, 0, timing)) {
+ (gd->fdt_blob, dev_of_offset(dev), 0, timing)) {
debug("%s: Failed to decode display timing\n", __func__);
return -EINVAL;
}
{
struct rk_lvds_priv *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int ret;
priv->regs = (void *)dev_get_addr(dev);
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
* clock so it is currently not possible to use more than one display
* device simultaneously.
*/
- port = fdt_subnode_offset(blob, dev->of_offset, "port");
+ port = fdt_subnode_offset(blob, dev_of_offset(dev), "port");
if (port < 0)
return -EINVAL;
for (node = fdt_first_subnode(blob, port);
struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
struct sandbox_sdl_plat *plat = dev_get_platdata(dev);
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int ret = 0;
plat->xres = fdtdec_get_int(blob, node, "xres", LCD_MAX_WIDTH);
struct tegra_lcd_priv *priv = dev_get_priv(dev);
const void *blob = gd->fdt_blob;
struct display_timing *timing;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int panel_node;
int rgb;
int ret;
{
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
const void *blob = gd->fdt_blob;
- int node = dev->of_offset;
+ int node = dev_of_offset(dev);
int rgb;
rgb = fdt_subnode_offset(blob, node, "rgb");
return ret;
}
- dc_ctlr = (struct dc_ctlr *)fdtdec_get_addr(blob, dev->of_offset,
+ dc_ctlr = (struct dc_ctlr *)fdtdec_get_addr(blob, dev_of_offset(dev),
"reg");
- if (fdtdec_decode_display_timing(blob, dev->of_offset, 0, timing)) {
+ if (fdtdec_decode_display_timing(blob, dev_of_offset(dev), 0, timing)) {
debug("%s: Failed to decode display timing\n", __func__);
return -EINVAL;
}
/* Use the first display controller */
debug("%s\n", __func__);
- node = dc_dev->of_offset;
+ node = dev_of_offset(dc_dev);
disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
tegra_dc_sor_enable_dc(disp_ctrl);
debug("%s\n", __func__);
/* Use the first display controller */
- node = dc_dev->of_offset;
+ node = dev_of_offset(dc_dev);
disp_ctrl = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg");
/* Sleep mode */
int node;
int ret;
- priv->base = (void *)fdtdec_get_addr(blob, dev->of_offset, "reg");
+ priv->base = (void *)fdtdec_get_addr(blob, dev_of_offset(dev), "reg");
node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_PMC);
if (node < 0) {
/* Returns non-zero if the device is active (probed and not removed) */
#define device_active(dev) ((dev)->flags & DM_FLAG_ACTIVATED)
+static inline int dev_of_offset(const struct udevice *dev)
+{
+ return dev->of_offset;
+}
+
+static inline void dev_set_of_offset(struct udevice *dev, int of_offset)
+{
+ dev->of_offset = of_offset;
+}
+
/**
* struct udevice_id - Lists the compatible strings supported by a driver
* @compatible: Compatible string
*/
ut_asserteq(0, uclass_get_device_by_seq(UCLASS_SPI, busnum, &bus));
ut_assertok(spi_cs_info(bus, cs, &info));
- of_offset = info.dev->of_offset;
+ of_offset = dev_of_offset(info.dev);
device_remove(info.dev);
device_unbind(info.dev);
{
struct dm_test_pdata *pdata = dev_get_platdata(dev);
- pdata->ping_add = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ pdata->ping_add = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"ping-add", -1);
- pdata->base = fdtdec_get_addr(gd->fdt_blob, dev->of_offset,
+ pdata->base = fdtdec_get_addr(gd->fdt_blob, dev_of_offset(dev),
"ping-expect");
return 0;
* want to test the code that sets that up
* (testfdt_drv_probe()).
*/
- base = fdtdec_get_addr(gd->fdt_blob, dev->of_offset,
+ base = fdtdec_get_addr(gd->fdt_blob, dev_of_offset(dev),
"ping-expect");
debug("dev=%d, base=%d: %s\n", i, base,
- fdt_get_name(gd->fdt_blob, dev->of_offset, NULL));
+ fdt_get_name(gd->fdt_blob, dev_of_offset(dev), NULL));
ut_assert(!dm_check_operations(uts, dev, base,
dev_get_priv(dev)));
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