ARM: tegra: add Jetson TK1 board

Jetson TK1 is an NVIDIA Tegra124 reference board, which shares much of
its design with Venice2.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2c3c773306b23532e6f3731946b48afbb753875c..55546152b94b3be201b266683cb5213a5d5c6b8b 100644 (file)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -22,6 +22,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
        tegra30-cardhu.dtb \
        tegra30-tec-ng.dtb \
        tegra114-dalmore.dtb \
+       tegra124-jetson-tk1.dtb \
        tegra124-venice2.dtb
 dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
        zynq-zc706.dtb \

diff --git a/arch/arm/dts/tegra124-jetson-tk1.dts b/arch/arm/dts/tegra124-jetson-tk1.dts
new file mode 100644 (file)
index 0000000..52e8c0e
--- /dev/null
+++ b/arch/arm/dts/tegra124-jetson-tk1.dts
@@ -0,0 +1,84 @@
+/dts-v1/;
+
+#include "tegra124.dtsi"
+
+/ {
+       model = "NVIDIA Jetson TK1";
+       compatible = "nvidia,jetson-tk1", "nvidia,tegra124";
+
+       aliases {
+               i2c0 = "/i2c@7000d000";
+               i2c1 = "/i2c@7000c000";
+               i2c2 = "/i2c@7000c400";
+               i2c3 = "/i2c@7000c500";
+               i2c4 = "/i2c@7000c700";
+               i2c5 = "/i2c@7000d100";
+               sdhci0 = "/sdhci@700b0600";
+               sdhci1 = "/sdhci@700b0400";
+               spi0 = "/spi@7000d400";
+               spi1 = "/spi@7000da00";
+               usb0 = "/usb@7d008000";
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0x80000000 0x80000000>;
+       };
+
+       i2c@7000c000 {
+               status = "okay";
+               clock-frequency = <100000>;
+       };
+
+       i2c@7000c400 {
+               status = "okay";
+               clock-frequency = <100000>;
+       };
+
+       i2c@7000c500 {
+               status = "okay";
+               clock-frequency = <100000>;
+       };
+
+       i2c@7000c700 {
+               status = "okay";
+               clock-frequency = <100000>;
+       };
+
+       i2c@7000d000 {
+               status = "okay";
+               clock-frequency = <400000>;
+       };
+
+       i2c@7000d100 {
+               status = "okay";
+               clock-frequency = <400000>;
+       };
+
+       spi@7000d400 {
+               status = "okay";
+               spi-max-frequency = <25000000>;
+       };
+
+       spi@7000da00 {
+               status = "okay";
+               spi-max-frequency = <25000000>;
+       };
+
+       sdhci@700b0400 {
+               status = "okay";
+               cd-gpios = <&gpio 170 1>; /* gpio PV2 */
+               power-gpios = <&gpio 136 0>; /* gpio PR0 */
+               bus-width = <4>;
+       };
+
+       sdhci@700b0600 {
+               status = "okay";
+               bus-width = <8>;
+       };
+
+       usb@7d008000 {
+               status = "okay";
+               nvidia,vbus-gpio = <&gpio 109 0>; /* gpio PN5, USB_VBUS_EN1 */
+       };
+};

diff --git a/board/nvidia/jetson-tk1/Makefile b/board/nvidia/jetson-tk1/Makefile
new file mode 100644 (file)
index 0000000..0f05411
--- /dev/null
+++ b/board/nvidia/jetson-tk1/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2014
+# NVIDIA Corporation <www.nvidia.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  += ../venice2/as3722_init.o
+obj-y  += jetson-tk1.o

diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c
new file mode 100644 (file)
index 0000000..f97aafa
--- /dev/null
+++ b/board/nvidia/jetson-tk1/jetson-tk1.c
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/pinmux.h>
+#include "pinmux-config-jetson-tk1.h"
+
+/*
+ * Routine: pinmux_init
+ * Description: Do individual peripheral pinmux configs
+ */
+void pinmux_init(void)
+{
+       pinmux_config_pingrp_table(jetson_tk1_pingrps,
+                                  ARRAY_SIZE(jetson_tk1_pingrps));
+
+       pinmux_config_drvgrp_table(jetson_tk1_drvgrps,
+                                  ARRAY_SIZE(jetson_tk1_drvgrps));
+}

diff --git a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
new file mode 100644 (file)
index 0000000..1adcae4
--- /dev/null
+++ b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
@@ -0,0 +1,227 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _PINMUX_CONFIG_JETSON_TK1_H_
+#define _PINMUX_CONFIG_JETSON_TK1_H_
+
+#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
+       {                                                       \
+               .pingrp         = PMUX_PINGRP_##_pingrp,        \
+               .func           = PMUX_FUNC_##_mux,             \
+               .pull           = PMUX_PULL_##_pull,            \
+               .tristate       = PMUX_TRI_##_tri,              \
+               .io             = PMUX_PIN_##_io,               \
+               .od             = PMUX_PIN_OD_##_od,            \
+               .rcv_sel        = PMUX_PIN_RCV_SEL_##_rcv_sel,  \
+               .lock           = PMUX_PIN_LOCK_DEFAULT,        \
+               .ioreset        = PMUX_PIN_IO_RESET_DEFAULT,    \
+       }
+
+static const struct pmux_pingrp_config jetson_tk1_pingrps[] = {
+       /*     pingrp,                 mux,          pull,   tri,      e_input, od,      rcv_sel */
+       PINCFG(CLK_32K_OUT_PA0,        SOC,          UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(UART3_CTS_N_PA1,        UARTC,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(DAP2_FS_PA2,            I2S1,         NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(DAP2_SCLK_PA3,          I2S1,         NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(DAP2_DIN_PA4,           I2S1,         NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(DAP2_DOUT_PA5,          I2S1,         NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC3_CLK_PA6,         SDMMC3,       NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(SDMMC3_CMD_PA7,         SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PB0,                    UARTD,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PB1,                    UARTD,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC3_DAT3_PB4,        SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC3_DAT2_PB5,        SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC3_DAT1_PB6,        SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC3_DAT0_PB7,        SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(UART3_RTS_N_PC0,        UARTC,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(UART2_TXD_PC2,          IRDA,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(UART2_RXD_PC3,          IRDA,         UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(GEN1_I2C_SCL_PC4,       I2C1,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+       PINCFG(GEN1_I2C_SDA_PC5,       I2C1,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+       PINCFG(PC7,                    RSVD1,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PG0,                    RSVD1,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PG1,                    RSVD1,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PG2,                    RSVD1,        DOWN,   NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PG3,                    RSVD1,        DOWN,   NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PG4,                    SPI4,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PG5,                    SPI4,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PG6,                    SPI4,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PG7,                    SPI4,         NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PH0,                    GMI,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PH1,                    PWM1,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PH2,                    GMI,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PH3,                    GMI,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PH4,                    RSVD2,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PH5,                    RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PH6,                    GMI,          UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PH7,                    GMI,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PI0,                    RSVD1,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PI1,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PI2,                    RSVD4,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PI3,                    SPI4,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PI4,                    GMI,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PI5,                    RSVD2,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PI6,                    RSVD1,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PI7,                    RSVD1,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PJ0,                    RSVD1,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PJ2,                    RSVD1,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(UART2_CTS_N_PJ5,        UARTB,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(UART2_RTS_N_PJ6,        UARTB,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PJ7,                    UARTD,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PK0,                    SOC,          UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PK1,                    RSVD4,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PK2,                    RSVD1,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PK3,                    GMI,          UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PK4,                    RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(SPDIF_OUT_PK5,          RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(SPDIF_IN_PK6,           RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PK7,                    UARTD,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DAP1_FS_PN0,            I2S0,         DOWN,   NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(DAP1_DIN_PN1,           I2S0,         DOWN,   NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(DAP1_DOUT_PN2,          SATA,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DAP1_SCLK_PN3,          I2S0,         DOWN,   NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(USB_VBUS_EN0_PN4,       USB,          UP,     NORMAL,   INPUT,   ENABLE,  DEFAULT),
+       PINCFG(USB_VBUS_EN1_PN5,       USB,          UP,     NORMAL,   INPUT,   ENABLE,  DEFAULT),
+       PINCFG(HDMI_INT_PN7,           RSVD1,        DOWN,   NORMAL,   INPUT,   DEFAULT, NORMAL),
+       PINCFG(ULPI_DATA7_PO0,         ULPI,         UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(ULPI_DATA0_PO1,         ULPI,         UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(ULPI_DATA1_PO2,         ULPI,         UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(ULPI_DATA2_PO3,         ULPI,         UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(ULPI_DATA3_PO4,         ULPI,         UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(ULPI_DATA4_PO5,         ULPI,         UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(ULPI_DATA5_PO6,         ULPI,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(ULPI_DATA6_PO7,         ULPI,         UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(DAP3_FS_PP0,            I2S2,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DAP3_DIN_PP1,           I2S2,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DAP3_DOUT_PP2,          RSVD4,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DAP3_SCLK_PP3,          RSVD3,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DAP4_FS_PP4,            I2S3,         DOWN,   NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(DAP4_DIN_PP5,           I2S3,         DOWN,   NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(DAP4_DOUT_PP6,          I2S3,         DOWN,   NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(DAP4_SCLK_PP7,          I2S3,         DOWN,   NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(KB_COL0_PQ0,            RSVD2,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(KB_COL1_PQ1,            RSVD2,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(KB_COL2_PQ2,            RSVD2,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(KB_COL3_PQ3,            KBC,          DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(KB_COL4_PQ4,            SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(KB_COL5_PQ5,            RSVD2,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(KB_COL6_PQ6,            RSVD2,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(KB_COL7_PQ7,            RSVD2,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(KB_ROW0_PR0,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(KB_ROW1_PR1,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(KB_ROW2_PR2,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(KB_ROW3_PR3,            SYS,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(KB_ROW4_PR4,            RSVD3,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(KB_ROW5_PR5,            RSVD3,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(KB_ROW6_PR6,            DISPLAYA_ALT, DOWN,   NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(KB_ROW7_PR7,            RSVD2,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(KB_ROW8_PS0,            RSVD2,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(KB_ROW9_PS1,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(KB_ROW10_PS2,           RSVD2,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(KB_ROW11_PS3,           RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(KB_ROW12_PS4,           RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(KB_ROW13_PS5,           RSVD2,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(KB_ROW14_PS6,           RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(KB_ROW15_PS7,           SOC,          UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(KB_ROW16_PT0,           RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(KB_ROW17_PT1,           RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(GEN2_I2C_SCL_PT5,       I2C2,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+       PINCFG(GEN2_I2C_SDA_PT6,       I2C2,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+       PINCFG(SDMMC4_CMD_PT7,         SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PU0,                    RSVD4,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PU1,                    RSVD1,        DOWN,   NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PU2,                    RSVD1,        DOWN,   NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PU3,                    GMI,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PU4,                    GMI,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PU5,                    GMI,          UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PU6,                    RSVD3,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PV0,                    RSVD1,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PV1,                    RSVD1,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC3_CD_N_PV2,        SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC1_WP_N_PV3,        SDMMC1,       DOWN,   TRISTATE, OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DDC_SCL_PV4,            I2C4,         NORMAL, NORMAL,   INPUT,   DEFAULT, NORMAL),
+       PINCFG(DDC_SDA_PV5,            I2C4,         NORMAL, NORMAL,   INPUT,   DEFAULT, NORMAL),
+       PINCFG(GPIO_W2_AUD_PW2,        RSVD2,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(GPIO_W3_AUD_PW3,        SPI6,         UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(DAP_MCLK1_PW4,          EXTPERIPH1,   NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(CLK2_OUT_PW5,           EXTPERIPH2,   NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(UART3_TXD_PW6,          UARTC,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(UART3_RXD_PW7,          UARTC,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(DVFS_PWM_PX0,           CLDVFS,       NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(GPIO_X1_AUD_PX1,        RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DVFS_CLK_PX2,           CLDVFS,       NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(GPIO_X3_AUD_PX3,        RSVD4,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(GPIO_X4_AUD_PX4,        GMI,          NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(GPIO_X5_AUD_PX5,        RSVD4,        UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(GPIO_X6_AUD_PX6,        GMI,          UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(GPIO_X7_AUD_PX7,        RSVD1,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(ULPI_CLK_PY0,           SPI1,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(ULPI_DIR_PY1,           SPI1,         DOWN,   NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(ULPI_NXT_PY2,           SPI1,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(ULPI_STP_PY3,           SPI1,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(SDMMC1_DAT3_PY4,        SDMMC1,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC1_DAT2_PY5,        SDMMC1,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC1_DAT1_PY6,        SDMMC1,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC1_DAT0_PY7,        SDMMC1,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC1_CLK_PZ0,         SDMMC1,       NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC1_CMD_PZ1,         SDMMC1,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PWR_I2C_SCL_PZ6,        I2CPWR,       NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+       PINCFG(PWR_I2C_SDA_PZ7,        I2CPWR,       NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+       PINCFG(SDMMC4_DAT0_PAA0,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC4_DAT1_PAA1,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC4_DAT2_PAA2,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC4_DAT3_PAA3,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC4_DAT4_PAA4,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC4_DAT5_PAA5,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC4_DAT6_PAA6,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC4_DAT7_PAA7,       SDMMC4,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PBB0,                   VIMCLK2_ALT,  NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(CAM_I2C_SCL_PBB1,       I2C3,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+       PINCFG(CAM_I2C_SDA_PBB2,       I2C3,         NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+       PINCFG(PBB3,                   VGP3,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PBB4,                   VGP4,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PBB5,                   RSVD3,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PBB6,                   RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PBB7,                   RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(CAM_MCLK_PCC0,          VI_ALT3,      NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PCC1,                   RSVD2,        DOWN,   NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(PCC2,                   RSVD2,        DOWN,   NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC4_CLK_PCC4,        SDMMC4,       NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(CLK2_REQ_PCC5,          RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(CLK3_OUT_PEE0,          EXTPERIPH3,   NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(CLK3_REQ_PEE1,          RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(DAP_MCLK1_REQ_PEE2,     SATA,         NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(HDMI_CEC_PEE3,          CEC,          NORMAL, NORMAL,   INPUT,   ENABLE,  DEFAULT),
+       PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(SDMMC3_CLK_LB_IN_PEE5,  SDMMC3,       UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(DP_HPD_PFF0,            DP,           UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(USB_VBUS_EN2_PFF1,      RSVD2,        NORMAL, NORMAL,   OUTPUT,  DISABLE, DEFAULT),
+       PINCFG(PFF2,                   RSVD2,        UP,     NORMAL,   INPUT,   DISABLE, DEFAULT),
+       PINCFG(CORE_PWR_REQ,           PWRON,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(CPU_PWR_REQ,            RSVD2,        NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(PWR_INT_N,              PMI,          UP,     NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(RESET_OUT_N,            RESET_OUT_N,  NORMAL, NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+       PINCFG(OWR,                    RSVD2,        DOWN,   TRISTATE, OUTPUT,  DEFAULT, NORMAL),
+       PINCFG(CLK_32K_IN,             RSVD2,        NORMAL, NORMAL,   INPUT,   DEFAULT, DEFAULT),
+       PINCFG(JTAG_RTCK,              RTCK,         UP,     NORMAL,   OUTPUT,  DEFAULT, DEFAULT),
+};
+
+#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+       {                                               \
+               .drvgrp = PMUX_DRVGRP_##_drvgrp,        \
+               .slwf   = _slwf,                        \
+               .slwr   = _slwr,                        \
+               .drvup  = _drvup,                       \
+               .drvdn  = _drvdn,                       \
+               .lpmd   = PMUX_LPMD_##_lpmd,            \
+               .schmt  = PMUX_SCHMT_##_schmt,          \
+               .hsm    = PMUX_HSM_##_hsm,              \
+       }
+
+static const struct pmux_drvgrp_config jetson_tk1_drvgrps[] = {
+};
+
+#endif /* PINMUX_CONFIG_JETSON_TK1_H */

diff --git a/board/nvidia/venice2/as3722_init.h b/board/nvidia/venice2/as3722_init.h
index 2a9e7cdf87215ad8a84c7d86ced35fb6cf4085c5..a7b24039f6aac2713806834eea0bfa0583cdd5ff 100644 (file)
--- a/board/nvidia/venice2/as3722_init.h
+++ b/board/nvidia/venice2/as3722_init.h
@@ -18,7 +18,11 @@
 #define AS3722_LDO6VOLTAGE_REG 0x16    /* VDD_SDMMC */
 #define AS3722_LDCONTROL_REG   0x4E
 
+#ifdef CONFIG_BOARD_JETSON_TK1
+#define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
+#else
 #define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG)
+#endif
 #define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG)
 
 #define AS3722_SD1VOLTAGE_DATA (0x3200 | AS3722_SD1VOLTAGE_REG)

diff --git a/boards.cfg b/boards.cfg
index b4203f1b576fee0b39dafd21706a3fb9073fea1c..7cd543b39dd38a668908c8d95ecbc020a1e4967c 100644 (file)
--- a/boards.cfg
+++ b/boards.cfg
@@ -381,6 +381,7 @@ Active  arm         armv7          zynq        xilinx          zynq
 Active  arm         armv7          zynq        xilinx          zynq                zynq_zc770_xm013                     zynq_zc770:ZC770_XM013                                                                                                            Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
 Active  arm         armv7          zynq        xilinx          zynq                zynq_zed                             -                                                                                                                                 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
 Active  arm         armv7:arm720t  tegra114    nvidia          dalmore             dalmore                              -                                                                                                                                 Tom Warren <twarren@nvidia.com>
+Active  arm         armv7:arm720t  tegra124    nvidia          jetson-tk1          jetson-tk1                           jetson-tk1:BOARD_JETSON_TK1=                                                                                                      Stephen Warren <swarren@nvidia.com>
 Active  arm         armv7:arm720t  tegra124    nvidia          venice2             venice2                              -                                                                                                                                 Tom Warren <twarren@nvidia.com>
 Active  arm         armv7:arm720t  tegra20     avionic-design  medcom-wide         medcom-wide                          -                                                                                                                                 Alban Bedel <alban.bedel@avionic-design.de>
 Active  arm         armv7:arm720t  tegra20     avionic-design  plutux              plutux                               -                                                                                                                                 Alban Bedel <alban.bedel@avionic-design.de>

diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h
new file mode 100644 (file)
index 0000000..6255750
--- /dev/null
+++ b/include/configs/jetson-tk1.h
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2013-2014
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <linux/sizes.h>
+
+#include "tegra124-common.h"
+
+/* Enable fdt support for Jetson TK1. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE     tegra124-jetson-tk1
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT                       "Tegra124 (Jetson TK1) # "
+#define CONFIG_TEGRA_BOARD_STRING      "NVIDIA Jetson TK1"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA_ENABLE_UARTD
+#define CONFIG_SYS_NS16550_COM1                NV_PA_APB_UARTD_BASE
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* I2C */
+#define CONFIG_SYS_I2C_TEGRA
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS         TEGRA_I2C_NUM_CONTROLLERS
+#define CONFIG_SYS_I2C_SPEED           100000
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET              (-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV         0
+#define CONFIG_SYS_MMC_ENV_PART                2
+
+/* SPI */
+#define CONFIG_TEGRA114_SPI            /* Compatible w/ Tegra114 SPI */
+#define CONFIG_TEGRA114_SPI_CTRLS      6
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED                24000000
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_SIZE          (4 << 20)
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */