/*
-* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
*
* See file CREDITS for list of people who contributed to this
* project.
#include <config.h>
/* General */
-#define TLB_VALID 0x00000200
+#define TLB_VALID 0x00000200
/* Supported page sizes */
-
-#define SZ_1K 0x00000000
-#define SZ_4K 0x00000010
-#define SZ_16K 0x00000020
-#define SZ_64K 0x00000030
-#define SZ_256K 0x00000040
-#define SZ_1M 0x00000050
-#define SZ_16M 0x00000070
-#define SZ_256M 0x00000090
+#define SZ_1K 0x00000000
+#define SZ_4K 0x00000010
+#define SZ_16K 0x00000020
+#define SZ_64K 0x00000030
+#define SZ_256K 0x00000040
+#define SZ_1M 0x00000050
+#define SZ_16M 0x00000070
+#define SZ_256M 0x00000090
/* Storage attributes */
-#define SA_W 0x00000800 /* Write-through */
-#define SA_I 0x00000400 /* Caching inhibited */
-#define SA_M 0x00000200 /* Memory coherence */
-#define SA_G 0x00000100 /* Guarded */
-#define SA_E 0x00000080 /* Endian */
+#define SA_W 0x00000800 /* Write-through */
+#define SA_I 0x00000400 /* Caching inhibited */
+#define SA_M 0x00000200 /* Memory coherence */
+#define SA_G 0x00000100 /* Guarded */
+#define SA_E 0x00000080 /* Endian */
/* Access control */
-#define AC_X 0x00000024 /* Execute */
-#define AC_W 0x00000012 /* Write */
-#define AC_R 0x00000009 /* Read */
+#define AC_X 0x00000024 /* Execute */
+#define AC_W 0x00000012 /* Write */
+#define AC_R 0x00000009 /* Read */
/* Some handy macros */
-
#define EPN(e) ((e) & 0xfffffc00)
-#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a) ( (a)&0x00000fbf )
+#define TLB0(epn,sz) ((EPN((epn)) | (sz) | TLB_VALID ))
+#define TLB1(rpn,erpn) (((rpn)&0xfffffc00) | (erpn))
+#define TLB2(a) ((a)&0x00000fbf)
-#define tlbtab_start\
- mflr r1 ;\
- bl 0f ;
+#define tlbtab_start \
+ mflr r1; \
+ bl 0f;
-#define tlbtab_end\
- .long 0, 0, 0 ; \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
+#define tlbtab_end \
+ .long 0, 0, 0; \
+0: mflr r0; \
+ mtlr r1; \
+ blr;
#define tlbentry(epn,sz,rpn,erpn,attr)\
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-/**************************************************************************
+/*
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
* entries. Rather than make broad assumptions in the cpu source tree,
* this table lets each board set things up however they like.
*
- * Pointer to the table is returned in r1
- *
- *************************************************************************/
+ * Pointer to the table is returned in r1
+ */
.section .bootpg,"ax"
.globl tlbtab
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
-/* . = env_offset;*/
-/* common/env_embedded.o(.text)*/
-
*(.text)
*(.fixup)
*(.got1)
/*
- * Copyright (C) 2003 Travis B. Sawyer <travis.sawyer@sandburst.com>
+ * Copyright (C) 2003 Travis B. Sawyer <travis.sawyer@sandburst.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* MA 02111-1307 USA
*/
-
#include <common.h>
#include <asm/processor.h>
#include <spd_sdram.h>
int board_early_init_f(void)
{
unsigned long sdrreg;
- /* TBS: Setup the GPIO access for the user LEDs */
+
+ /* TBS: Setup the GPIO access for the user LEDs */
mfsdr(sdr_pfc0, sdrreg);
mtsdr(sdr_pfc0, (sdrreg & ~0x00000100) | 0x00000E00);
out32(CONFIG_SYS_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3));
LED2_OFF();
LED3_OFF();
- /*--------------------------------------------------------------------
- * Setup the external bus controller/chip selects
- *-------------------------------------------------------------------*/
- mtebc (pb0ap, 0x04055200); /* 16MB Strata FLASH */
- mtebc (pb0cr, 0xff098000); /* BAS=0xff0 16MB R/W 8-bit */
- mtebc (pb1ap, 0x04055200); /* 512KB Socketed AMD FLASH */
- mtebc (pb1cr, 0xfe018000); /* BAS=0xfe0 1MB R/W 8-bit */
+ /* Setup the external bus controller/chip selects */
+ mtebc(pb0ap, 0x04055200); /* 16MB Strata FLASH */
+ mtebc(pb0cr, 0xff098000); /* BAS=0xff0 16MB R/W 8-bit */
+ mtebc(pb1ap, 0x04055200); /* 512KB Socketed AMD FLASH */
+ mtebc(pb1cr, 0xfe018000); /* BAS=0xfe0 1MB R/W 8-bit */
- /*--------------------------------------------------------------------
- * Setup the interrupt controller polarities, triggers, etc.
- *-------------------------------------------------------------------*/
/*
+ * Setup the interrupt controller polarities, triggers, etc.
+ *
* Because of the interrupt handling rework to handle 440GX interrupts
* with the common code, we needed to change names of the UIC registers.
* Here the new relationship:
* UIC2 UIC1
* UIC3 UIC2
*/
- mtdcr (uic1sr, 0xffffffff); /* clear all */
- mtdcr (uic1er, 0x00000000); /* disable all */
- mtdcr (uic1cr, 0x00000003); /* SMI & UIC1 crit are critical */
- mtdcr (uic1pr, 0xfffffe00); /* per ref-board manual */
- mtdcr (uic1tr, 0x01c00000); /* per ref-board manual */
- mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic1sr, 0xffffffff); /* clear all */
-
- mtdcr (uic2sr, 0xffffffff); /* clear all */
- mtdcr (uic2er, 0x00000000); /* disable all */
- mtdcr (uic2cr, 0x00000000); /* all non-critical */
- mtdcr (uic2pr, 0xffffc0ff); /* per ref-board manual */
- mtdcr (uic2tr, 0x00ff8000); /* per ref-board manual */
- mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic2sr, 0xffffffff); /* clear all */
-
- mtdcr (uic3sr, 0xffffffff); /* clear all */
- mtdcr (uic3er, 0x00000000); /* disable all */
- mtdcr (uic3cr, 0x00000000); /* all non-critical */
- mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */
- mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */
- mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
- mtdcr (uic3sr, 0xffffffff); /* clear all */
-
- mtdcr (uic0sr, 0xfc000000); /* clear all */
- mtdcr (uic0er, 0x00000000); /* disable all */
- mtdcr (uic0cr, 0x00000000); /* all non-critical */
- mtdcr (uic0pr, 0xfc000000); /* */
- mtdcr (uic0tr, 0x00000000); /* */
- mtdcr (uic0vr, 0x00000001); /* */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+ mtdcr(uic1er, 0x00000000); /* disable all */
+ mtdcr(uic1cr, 0x00000003); /* SMI & UIC1 crit are critical */
+ mtdcr(uic1pr, 0xfffffe00); /* per ref-board manual */
+ mtdcr(uic1tr, 0x01c00000); /* per ref-board manual */
+ mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(uic1sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
+ mtdcr(uic2er, 0x00000000); /* disable all */
+ mtdcr(uic2cr, 0x00000000); /* all non-critical */
+ mtdcr(uic2pr, 0xffffc0ff); /* per ref-board manual */
+ mtdcr(uic2tr, 0x00ff8000); /* per ref-board manual */
+ mtdcr(uic2vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(uic2sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic3sr, 0xffffffff); /* clear all */
+ mtdcr(uic3er, 0x00000000); /* disable all */
+ mtdcr(uic3cr, 0x00000000); /* all non-critical */
+ mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
+ mtdcr(uic3tr, 0x00ff8c0f); /* per ref-board manual */
+ mtdcr(uic3vr, 0x00000001); /* int31 highest, base=0x000 */
+ mtdcr(uic3sr, 0xffffffff); /* clear all */
+
+ mtdcr(uic0sr, 0xfc000000); /* clear all */
+ mtdcr(uic0er, 0x00000000); /* disable all */
+ mtdcr(uic0cr, 0x00000000); /* all non-critical */
+ mtdcr(uic0pr, 0xfc000000); /* */
+ mtdcr(uic0tr, 0x00000000); /* */
+ mtdcr(uic0vr, 0x00000001); /* */
LED0_ON();
-
return 0;
}
-int checkboard (void)
+int checkboard(void)
{
- printf ("Board: XES XPedite1000 440GX\n");
+ printf("Board: XES XPedite1000 440GX\n");
- return (0);
+ return 0;
}
-
-phys_size_t initdram (int board_type)
+phys_size_t initdram(int board_type)
{
return spd_sdram();
}
-
-/*************************************************************************
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
+/*
+ * This routine is called just prior to registering the hose and gives
+ * the board the opportunity to check things. Returning a value of zero
+ * indicates that things are bad & PCI initialization should be aborted.
*
- ************************************************************************/
+ * Different boards may wish to customize the pci controller structure
+ * (add regions, override default access routines, etc) or perform
+ * certain pre-initialization actions.
+ */
+
#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller * hose )
+int pci_pre_init(struct pci_controller * hose)
{
unsigned long strap;
+
/* See if we're supposed to setup the pci */
mfsdr(sdr_sdstp1, strap);
- if ((strap & 0x00010000) == 0) {
- return (0);
- }
+ if ((strap & 0x00010000) == 0)
+ return 0;
#if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV)
/* Setup System Device Register PCIX0_XCR */
strap &= 0x0f000000;
mtsdr(sdr_xcr, strap);
#endif
+
return 1;
}
#endif /* defined(CONFIG_PCI) */
-/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
+/*
+ * The bootstrap configuration provides default settings for the pci
+ * inbound map (PIM). But the bootstrap config choices are limited and
+ * may not be sufficient for a given board.
+ */
+void pci_target_init(struct pci_controller * hose)
{
- /*--------------------------------------------------------------------------+
- * Disable everything
- *--------------------------------------------------------------------------*/
- out32r( PCIX0_PIM0SA, 0 ); /* disable */
- out32r( PCIX0_PIM1SA, 0 ); /* disable */
- out32r( PCIX0_PIM2SA, 0 ); /* disable */
- out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
-
- /*--------------------------------------------------------------------------+
+ /* Disable everything */
+ out32r(PCIX0_PIM0SA, 0);
+ out32r(PCIX0_PIM1SA, 0);
+ out32r(PCIX0_PIM2SA, 0);
+ out32r(PCIX0_EROMBA, 0); /* disable expansion rom */
+
+ /*
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB.
- *--------------------------------------------------------------------------*/
- out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
- out32r( PCIX0_PIM0LAH, 0 );
- out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
+ */
+ out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
+ out32r(PCIX0_PIM0LAH, 0);
+ out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
- out32r( PCIX0_BAR0, 0 );
+ out32r(PCIX0_BAR0, 0);
- /*--------------------------------------------------------------------------+
- * Program the board's subsystem id/vendor id
- *--------------------------------------------------------------------------*/
- out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
- out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
+ /* Program the board's subsystem id/vendor id */
+ out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+ out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
- out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+ out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
}
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-/*************************************************************************
- * is_pci_host
- *
- * This routine is called to determine if a pci scan should be
- * performed. With various hardware environments (especially cPCI and
- * PPMC) it's insufficient to depend on the state of the arbiter enable
- * bit in the strap register, or generic host/adapter assumptions.
- *
- * Rather than hard-code a bad assumption in the general 440 code, the
- * 440 pci code requires the board to decide at runtime.
- *
- * Return 0 for adapter mode, non-zero for host (monarch) mode.
+#if defined(CONFIG_PCI)
+/*
+ * This routine is called to determine if a pci scan should be
+ * performed. With various hardware environments (especially cPCI and
+ * PPMC) it's insufficient to depend on the state of the arbiter enable
+ * bit in the strap register, or generic host/adapter assumptions.
*
+ * Rather than hard-code a bad assumption in the general 440 code, the
+ * 440 pci code requires the board to decide at runtime.
*
- ************************************************************************/
-#if defined(CONFIG_PCI)
+ * Return 0 for adapter mode, non-zero for host (monarch) mode.
+ */
int is_pci_host(struct pci_controller *hose)
{
return ((in32(CONFIG_SYS_GPIO_BASE + 0x1C) & 0x00000800) == 0);
*/
int post_hotkeys_pressed(void)
{
-
- return (ctrlc());
+ return ctrlc();
}
-void post_word_store (ulong a)
+void post_word_store(ulong a)
{
volatile ulong *save_addr =
(volatile ulong *)(CONFIG_SYS_POST_WORD_ADDR);
*save_addr = a;
}
-ulong post_word_load (void)
+ulong post_word_load(void)
{
volatile ulong *save_addr =
(volatile ulong *)(CONFIG_SYS_POST_WORD_ADDR);
return *save_addr;
}
-#endif
\ No newline at end of file
+#endif
* MA 02111-1307 USA
*/
-/************************************************************************
+/*
* config for XPedite1000 from XES Inc.
* Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com>
* (C) Copyright 2003 Sandburst Corporation
* board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
- ***********************************************************************/
+ */
#ifndef __CONFIG_H
#define __CONFIG_H
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
+/* High Level Configuration Options */
#define CONFIG_XPEDITE1K 1 /* Board is XPedite 1000 */
-#define CONFIG_4xx 1 /* ... PPC4xx family */
+#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_440 1
#define CONFIG_440GX 1 /* 440 GX */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
-
/* POST support */
-#define CONFIG_POST (CONFIG_SYS_POST_RTC | \
+#define CONFIG_POST (CONFIG_SYS_POST_RTC | \
CONFIG_SYS_POST_I2C)
-/*-----------------------------------------------------------------------
+/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */
+ */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
-#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
-#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
-#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
+#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
+#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
-#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
-#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
+#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
+#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
-#define USR_LED0 0x00000080
-#define USR_LED1 0x00000100
-#define USR_LED2 0x00000200
-#define USR_LED3 0x00000400
+#define USR_LED0 0x00000080
+#define USR_LED1 0x00000100
+#define USR_LED2 0x00000200
+#define USR_LED3 0x00000400
#ifndef __ASSEMBLY__
extern unsigned long in32(unsigned int);
#define LED3_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED3))
#endif
-/*-----------------------------------------------------------------------
- * Initial RAM & stack pointer (placed in internal SRAM)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-
+/* Initial RAM & stack pointer (placed in internal SRAM) */
+#define CONFIG_SYS_TEMP_STACK_OCM 1
+#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
+#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc */
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
+/* Serial Port */
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_BAUDRATE 9600
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
+/* RTC: STMicro M41T00 */
+#define CONFIG_RTC_M41T11 1
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_SYS_M41T11_BASE_YEAR 2000
-/*-----------------------------------------------------------------------
- * NVRAM/RTC
- *
- * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
- * The DS1743 code assumes this condition (i.e. -- it assumes the base
- * address for the RTC registers is:
- *
- * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
- *
- *----------------------------------------------------------------------*/
-/* TBS: Xpedite 1000 has STMicro M41T00 via IIC */
-#define CONFIG_RTC_M41T11 1
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR 2000
-
-/*-----------------------------------------------------------------------
+/*
* FLASH related
- *----------------------------------------------------------------------*/
+ */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-/*-----------------------------------------------------------------------
- * DDR SDRAM
- *----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
-#define SPD_EEPROM_ADDRESS {0x54} /* SPD i2c spd addresses */
-#define CONFIG_VERY_BIG_RAM 1
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+/* DDR SDRAM */
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
+#define SPD_EEPROM_ADDRESS {0x54} /* SPD i2c spd addresses */
+#define CONFIG_VERY_BIG_RAM 1
+
+/* I2C */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7f
-#define CONFIG_SYS_I2C_NOPROBES {0x55,0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x69} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_NOPROBES {0x55,0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x69}
-/*-----------------------------------------------------------------------
- * Environment
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_EEPROM 1
-#define CONFIG_ENV_SIZE 0x100 /* Size of Environment vars */
+/* Environment */
+#define CONFIG_ENV_IS_IN_EEPROM 1
+#define CONFIG_ENV_SIZE 0x100 /* Size of Environment vars */
#define CONFIG_ENV_OFFSET 0x100
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* this is actually the second page of the eeprom */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CONFIG_BOOTARGS "root=/dev/hda1 "
-#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
-#define CONFIG_BOOTDELAY 5 /* disable autoboot */
+#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
+#define CONFIG_BOOTDELAY 5 /* disable autoboot */
#define CONFIG_BAUDRATE 9600
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address phy0 not populated */
#define CONFIG_PHY1_ADDR 1 /* PHY address phy1 not populated */
#define CONFIG_PHY2_ADDR 4 /* PHY address phy2 */
#define CONFIG_PHY3_ADDR 8 /* PHY address phy3 */
#define CONFIG_NET_MULTI 1
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
-#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
-
-#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
-#define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */
-#define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */
+#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
+#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
+#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
+#define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */
+#define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */
-/*
- * BOOTP options
- */
+/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
-
/*
- * Command line configuration.
+ * Command line configuration
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_FAT
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
+#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
+/*
+ * PCI
*/
/* General PCI */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
/* Board-specific PCI */
-#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
-
+#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
-#define CONFIG_SYS_PCI_FORCE_PCI_CONV /* Force PCI Conventional Mode */
+#define CONFIG_SYS_PCI_FORCE_PCI_CONV /* Force PCI Conventional Mode */
+
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
/*
* Internal Definitions
- *
- * Boot Flags
*/
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
projects / u-boot.git / commitdiff