[ppc4xx] Fix problem with NAND booting on AMCC Acadia

The latest changes showed a problem with the location of the NAND-SPL
image in the OCM and the init-data area (incl. cache). This patch
fixes this problem.

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/board/amcc/acadia/Makefile b/board/amcc/acadia/Makefile
index ddbcb8091f73738c60b460ecc506f8f3798f8974..c56b2733a93d1ec3edfb1c0d22fc96306375df5d 100644 (file)
--- a/board/amcc/acadia/Makefile
+++ b/board/amcc/acadia/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB    = $(obj)lib$(BOARD).a
 
-COBJS  = $(BOARD).o cmd_acadia.o cpr.o memory.o
+COBJS  = $(BOARD).o cmd_acadia.o memory.o pll.o
 SOBJS  =
 
 SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)

diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c
index 46d63e6308bf2a55f19f12cbd735a0fcfbfdffbe..0f54025fb2ece02a88c8ae2403f67bcddebd8d60 100644 (file)
--- a/board/amcc/acadia/acadia.c
+++ b/board/amcc/acadia/acadia.c
@@ -55,10 +55,12 @@ int board_early_init_f(void)
 {
        unsigned int reg;
 
+#if !defined(CONFIG_NAND_U_BOOT)
        /* don't reinit PLL when booting via I2C bootstrap option */
        mfsdr(SDR_PINSTP, reg);
        if (reg != 0xf0000000)
                board_pll_init_f();
+#endif
 
        acadia_gpio_init();
 

diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c
index 25904d3b94a9680ff995ce6927effefc37ca28e3..9346d2c52fb969590a7c1fbedb580081cf5d5dff 100644 (file)
--- a/board/amcc/acadia/memory.c
+++ b/board/amcc/acadia/memory.c
@@ -31,6 +31,8 @@
 #include <asm/io.h>
 #include <asm/gpio.h>
 
+extern void board_pll_init_f(void);
+
 /*
  * sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
  */
@@ -67,6 +69,15 @@ static void cram_bcr_write(u32 wr_val)
 
 long int initdram(int board_type)
 {
+#if defined(CONFIG_NAND_SPL)
+       u32 reg;
+
+       /* don't reinit PLL when booting via I2C bootstrap option */
+       mfsdr(SDR_PINSTP, reg);
+       if (reg != 0xf0000000)
+               board_pll_init_f();
+#endif
+
 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
        int i;
        u32 val;

diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index e135220f6d00b59f4657c65765a9e983149f2ec4..16df1e7b35f923f0fc9df2988a1550cf6f0944e4 100644 (file)
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -564,7 +564,7 @@ ProgramCheck:
        STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
        STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
        STD_EXCEPTION(0xa00, APU, UnknownException)
-#endif 
+#endif
        STD_EXCEPTION(0xc00, SystemCall, UnknownException)
 
 #ifdef CONFIG_440
@@ -889,7 +889,7 @@ _start:
         */
        lis     r3,CFG_OCM_DATA_ADDR@h  /* OCM location */
        ori     r3,r3,CFG_OCM_DATA_ADDR@l
-       ori     r3,r3,0x8270    /* 32K Offset, 16K for Bank 1, R/W/Enable */
+       ori     r3,r3,0x0270            /* 16K for Bank 1, R/W/Enable */
        mtdcr   ocmplb3cr1,r3           /* Set PLB Access */
        ori     r3,r3,0x4000            /* Add 0x4000 for bank 2 */
        mtdcr   ocmplb3cr2,r3           /* Set PLB Access */
@@ -1623,7 +1623,7 @@ trap_init:
 
        li      r7, .L_APU - _start + _START_OFFSET
         bl      trap_reloc
-        
+
        li      r7, .L_InstructionTLBError - _start + _START_OFFSET
         bl      trap_reloc
 

diff --git a/include/configs/acadia.h b/include/configs/acadia.h
index 0f447b004a03c2b23c18fc948aed9a63b41f29a9..517d130d5cad933aa27b9e998ed5174b675fbba8 100644 (file)
--- a/include/configs/acadia.h
+++ b/include/configs/acadia.h
@@ -75,7 +75,7 @@
 #define CFG_TEMP_STACK_OCM     1               /* OCM as init ram      */
 
 /* On Chip Memory location */
-#define CFG_OCM_DATA_ADDR      0xF8000000
+#define CFG_OCM_DATA_ADDR      0xf8000000
 #define CFG_OCM_DATA_SIZE      0x4000                  /* 16K of onchip SRAM           */
 #define CFG_INIT_RAM_ADDR      CFG_OCM_DATA_ADDR       /* inside of SRAM               */
 #define CFG_INIT_RAM_END       CFG_OCM_DATA_SIZE       /* End of used area in RAM      */
@@ -159,7 +159,7 @@
  */
 #define CFG_NAND_BOOT_SPL_SRC  0xfffff000      /* SPL location                 */
 #define CFG_NAND_BOOT_SPL_SIZE (4 << 10)       /* SPL size                     */
-#define CFG_NAND_BOOT_SPL_DST  (CFG_OCM_DATA_ADDR + (12 << 10)) /* Copy SPL here*/
+#define CFG_NAND_BOOT_SPL_DST  (CFG_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/
 #define CFG_NAND_U_BOOT_DST    0x01000000      /* Load NUB to this addr        */
 #define CFG_NAND_U_BOOT_START  CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
 #define CFG_NAND_BOOT_SPL_DELTA        (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)

diff --git a/nand_spl/board/amcc/acadia/Makefile b/nand_spl/board/amcc/acadia/Makefile
index 0d6828a76fbcfef3e9509fffc77e7736370d74ea..926476f91b02f2c238a02793e64b3e3784a01d52 100644 (file)
--- a/nand_spl/board/amcc/acadia/Makefile
+++ b/nand_spl/board/amcc/acadia/Makefile
@@ -30,7 +30,7 @@ AFLAGS        += -DCONFIG_NAND_SPL
 CFLAGS += -DCONFIG_NAND_SPL
 
 SOBJS  = start.o resetvec.o
-COBJS  = gpio.o nand_boot.o nand_ecc.o memory.o ndfc.o
+COBJS  = gpio.o nand_boot.o nand_ecc.o memory.o ndfc.o pll.o
 
 SRCS   := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
 OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS))
@@ -39,7 +39,8 @@ LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
 
 nandobj        := $(OBJTREE)/nand_spl/
 
-ALL    = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+ALL    = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin \
+       $(nandobj)System.map
 
 all:   $(obj).depend $(ALL)
 
@@ -54,6 +55,11 @@ $(nandobj)u-boot-spl:        $(OBJS)
                -Map $(nandobj)u-boot-spl.map \
                -o $(nandobj)u-boot-spl
 
+$(nandobj)System.map:  $(nandobj)u-boot-spl
+               @$(NM) $< | \
+               grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
+               sort > $(nandobj)System.map
+
 # create symbolic links for common files
 
 # from cpu directory
@@ -78,6 +84,10 @@ $(obj)memory.c:
        @rm -f $(obj)memory.c
        ln -s $(SRCTREE)/board/amcc/acadia/memory.c $(obj)memory.c
 
+$(obj)pll.c:
+       @rm -f $(obj)pll.c
+       ln -s $(SRCTREE)/board/amcc/acadia/pll.c $(obj)pll.c
+
 # from nand_spl directory
 $(obj)nand_boot.c:
        @rm -f $(obj)nand_boot.c

diff --git a/nand_spl/board/amcc/acadia/config.mk b/nand_spl/board/amcc/acadia/config.mk
index 55069b4dfeaee783ed785c08a1a9284b2186686a..3b140fa7e8d0da760e6be58f88bb72ba154f77b1 100644 (file)
--- a/nand_spl/board/amcc/acadia/config.mk
+++ b/nand_spl/board/amcc/acadia/config.mk
@@ -32,11 +32,11 @@
 # We will copy this SPL into internal SRAM in start.S. So we set
 # TEXT_BASE to starting address in internal SRAM here.
 #
-TEXT_BASE = 0xF8003000
+TEXT_BASE = 0xf8004000
 
 # PAD_TO used to generate a 16kByte binary needed for the combined image
 # -> PAD_TO = TEXT_BASE + 0x4000
-PAD_TO = 0xF8007000
+PAD_TO = 0xf8008000
 
 ifeq ($(debug),1)
 PLATFORM_CPPFLAGS += -DDEBUG

diff --git a/nand_spl/board/amcc/acadia/u-boot.lds b/nand_spl/board/amcc/acadia/u-boot.lds
index 018def1faba318cf616867936d866862c47542ce..a07a773e011fd9097300db37db3364f0d0d2019a 100644 (file)
--- a/nand_spl/board/amcc/acadia/u-boot.lds
+++ b/nand_spl/board/amcc/acadia/u-boot.lds
@@ -24,7 +24,7 @@
 OUTPUT_ARCH(powerpc:common)
 SECTIONS
 {
-  .resetvec 0xF8003FFC :
+  .resetvec 0xf8004ffc :
   {
     *(.resetvec)
   } = 0xffff