ls102xa: dcu: Add platform support for DCU on LS1021AQDS board

This patch adds the CH7301 HDMI options and the common configuration
for DCU on LS1021AQDS board.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Cc: Jason Jin <Jason.Jin@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile
index 3b6903c83bcd8b64bda657f041fe778d3687d4d2..ab0234412cb88b7d3c9537eea771c327190383ea 100644 (file)
--- a/board/freescale/ls1021aqds/Makefile
+++ b/board/freescale/ls1021aqds/Makefile
@@ -7,3 +7,4 @@
 obj-y += ls1021aqds.o
 obj-y += ddr.o
 obj-y += eth.o
+obj-$(CONFIG_FSL_DCU_FB) += dcu.o

diff --git a/board/freescale/ls1021aqds/dcu.c b/board/freescale/ls1021aqds/dcu.c
new file mode 100644 (file)
index 0000000..90f5bc0
--- /dev/null
+++ b/board/freescale/ls1021aqds/dcu.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * FSL DCU Framebuffer driver
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_dcu_fb.h>
+#include <i2c.h>
+#include "div64.h"
+#include "../common/diu_ch7301.h"
+#include "ls1021aqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int select_i2c_ch_pca9547(u8 ch)
+{
+       int ret;
+
+       ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+       if (ret) {
+               puts("PCA: failed to select proper channel\n");
+               return ret;
+       }
+
+       return 0;
+}
+
+unsigned int dcu_set_pixel_clock(unsigned int pixclock)
+{
+       unsigned long long div;
+
+       div = (unsigned long long)(gd->bus_clk / 1000);
+       div *= (unsigned long long)pixclock;
+       do_div(div, 1000000000);
+
+       return div;
+}
+
+int platform_dcu_init(unsigned int xres, unsigned int yres,
+                     const char *port,
+                     struct fb_videomode *dcu_fb_videomode)
+{
+       const char *name;
+       unsigned int pixel_format;
+       int ret;
+       u8 ch;
+
+       /* Mux I2C3+I2C4 as HSYNC+VSYNC */
+       ret = i2c_read(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
+                      1, &ch, 1);
+       if (ret) {
+               printf("Error: failed to read I2C @%02x\n",
+                      CONFIG_SYS_I2C_QIXIS_ADDR);
+               return ret;
+       }
+       ch &= 0x1F;
+       ch |= 0xA0;
+       ret = i2c_write(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
+                       1, &ch, 1);
+       if (ret) {
+               printf("Error: failed to write I2C @%02x\n",
+                      CONFIG_SYS_I2C_QIXIS_ADDR);
+               return ret;
+       }
+
+       if (strncmp(port, "hdmi", 4) == 0) {
+               unsigned long pixval;
+
+               name = "HDMI";
+
+               pixval = 1000000000 / dcu_fb_videomode->pixclock;
+               pixval *= 1000;
+
+               i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
+               select_i2c_ch_pca9547(I2C_MUX_CH_CH7301);
+               diu_set_dvi_encoder(pixval);
+               select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+       } else {
+               return 0;
+       }
+
+       printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
+
+       pixel_format = 32;
+       fsl_dcu_init(xres, yres, pixel_format);
+
+       return 0;
+}

diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 0a3252effe89376602033e57e1f04b682eb703c5..691e993650d854b4207776a096209fa6de02a185 100644 (file)
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -193,6 +193,10 @@ int board_early_init_f(void)
        out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
 #endif
 
+#ifdef CONFIG_FSL_DCU_FB
+       out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
+#endif
+
        /* Workaround for the issue that DDR could not respond to
         * barrier transaction which is generated by executing DSB/ISB
         * instruction. Set CCI-400 control override register to

diff --git a/board/freescale/ls1021aqds/ls1021aqds_qixis.h b/board/freescale/ls1021aqds/ls1021aqds_qixis.h
index 09b3be2f9c2447a48b20a23553a9f2cba4af4f04..8e482eb0b075f07e7a197c08bb75c7549ec4bfce 100644 (file)
--- a/board/freescale/ls1021aqds/ls1021aqds_qixis.h
+++ b/board/freescale/ls1021aqds/ls1021aqds_qixis.h
@@ -32,4 +32,6 @@
 
 #define QIXIS_SRDS1CLK_100             0x0
 
+#define QIXIS_DCU_BRDCFG5              0x55
+
 #endif

diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 8dc04f2e574bd40eee24a31605a245b0373a4a16..8b757daef0a3a292cb7ba1fd5b57072e84618d6f 100644 (file)
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -385,6 +385,7 @@ unsigned long get_board_ddr_clk(void);
  */
 #define I2C_MUX_PCA_ADDR_PRI           0x77
 #define I2C_MUX_CH_DEFAULT             0x8
+#define I2C_MUX_CH_CH7301              0xC
 
 /*
  * MMC
@@ -426,6 +427,25 @@ unsigned long get_board_ddr_clk(void);
 #endif
 #endif
 
+/*
+ * Video
+ */
+#define CONFIG_FSL_DCU_FB
+
+#ifdef CONFIG_FSL_DCU_FB
+#define CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+
+#define CONFIG_FSL_DIU_CH7301
+#define CONFIG_SYS_I2C_DVI_BUS_NUM     0
+#define CONFIG_SYS_I2C_QIXIS_ADDR      0x66
+#define CONFIG_SYS_I2C_DVI_ADDR                0x75
+#endif
+
 /*
  * eTSEC
  */