sunxi: mmc: Add support for sun9i (A80)

The clocks on the A80 are hooked up slightly different, add support for this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
index 537f1455643cc5ffae3d998599f3b941d2244568..74833b51d1285e12db5865946eb6a34526c645bf 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/mmc.h
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -43,10 +43,11 @@ struct sunxi_mmc {
        u32 chda;               /* 0x90 */
        u32 cbda;               /* 0x94 */
        u32 res1[26];
-#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
+    defined(CONFIG_MACH_SUN9I)
        u32 res2[64];
 #endif
-       u32 fifo;               /* 0x100 (0x200 on sun6i) FIFO access address */
+       u32 fifo;               /* 0x100 / 0x200 FIFO access address */
 };
 
 #define SUNXI_MMC_CLK_POWERSAVE                (0x1 << 17)
@@ -123,5 +124,8 @@ struct sunxi_mmc {
 #define SUNXI_MMC_IDIE_TXIRQ           (0x1 << 0)
 #define SUNXI_MMC_IDIE_RXIRQ           (0x1 << 1)
 
+#define SUNXI_MMC_COMMON_CLK_GATE              (1 << 16)
+#define SUNXI_MMC_COMMON_RESET                 (1 << 18)
+
 struct mmc *sunxi_mmc_init(int sdc_no);
 #endif /* _SUNXI_MMC_H */

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 1d484b83cf0309ccb9218d4db10f37454419224c..510479516b80432328b26ad827788afd4769f82d 100644 (file)
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -89,8 +89,13 @@ static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz)
                pll = CCM_MMC_CTRL_OSCM24;
                pll_hz = 24000000;
        } else {
+#ifdef CONFIG_MACH_SUN9I
+               pll = CCM_MMC_CTRL_PLL_PERIPH0;
+               pll_hz = clock_get_pll4_periph0();
+#else
                pll = CCM_MMC_CTRL_PLL6;
                pll_hz = clock_get_pll6();
+#endif
        }
 
        div = pll_hz / hz;
@@ -146,10 +151,16 @@ static int mmc_clk_io_on(int sdc_no)
        /* config ahb clock */
        setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
 
-#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
+    defined(CONFIG_MACH_SUN9I)
        /* unassert reset */
        setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
 #endif
+#if defined(CONFIG_MACH_SUN9I)
+       /* sun9i has a mmc-common module, also set the gate and reset there */
+       writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
+              SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
+#endif
 
        return mmc_set_mod_clk(mmchost, 24000000);
 }
@@ -439,7 +450,8 @@ struct mmc *sunxi_mmc_init(int sdc_no)
        cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
        cfg->host_caps = MMC_MODE_4BIT;
        cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
-#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I)
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \
+    defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN9I)
        cfg->host_caps |= MMC_MODE_HC;
 #endif
        cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;