arm: rmobile: lager: Fix change of the CPU frequency

The change of the CPU frequency is waited for until PLL0ST of the PLLECR is
set to 1.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

diff --git a/arch/arm/include/asm/arch-rmobile/rcar-base.h b/arch/arm/include/asm/arch-rmobile/rcar-base.h
index 027e9b1b1453ea19033a7ee4c814843978d21352..9c1439b76467b940ca4d194aaef0b476917dea2f 100644 (file)
--- a/arch/arm/include/asm/arch-rmobile/rcar-base.h
+++ b/arch/arm/include/asm/arch-rmobile/rcar-base.h
@@ -385,6 +385,8 @@
 #define PLL0CR                 0xE61500D8
 #define PLL0_STC_MASK          0x7F000000
 #define PLL0_STC_BIT           24
+#define PLLECR                 0xE61500D0
+#define PLL0ST                 0x100
 
 #ifndef __ASSEMBLY__
 #include <asm/types.h>

diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c
index 5302839b33a9c960916c6910f93f65d5adeef2ca..1fc5833ebebb73d99118cca7046951e5eb9b2b55 100644 (file)
--- a/board/renesas/lager/lager.c
+++ b/board/renesas/lager/lager.c
@@ -36,9 +36,14 @@ void s_init(void)
 
        /* CPU frequency setting. Set to 1.4GHz */
        if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
+               u32 stat = 0;
                u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
                        << PLL0_STC_BIT;
                clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+
+               do {
+                       stat = readl(PLLECR) & PLL0ST;
+               } while (stat == 0x0);
        }
 
        /* QoS(Quality-of-Service) Init */