arm: dts: imx8mm-beacon: Resync dtsi with Kernel 5.17-rc1

Resync the SOM and baseboar files with the device trees that will
be included in 5.17-RC1 when it's cut.  This will improve pinmuxing
for USDHC1 and add USB functionality.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>

diff --git a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
index d6b9dedd168f1f80ae4b83df64bede36a038f8e5..4097a66163b2a7a41f796b846bc13b71af41a174 100644 (file)
--- a/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
+++ b/arch/arm/dts/imx8mm-beacon-baseboard.dtsi
@@ -43,6 +43,17 @@
                enable-active-high;
        };
 
+       reg_usbotg1: regulator-usbotg1 {
+               compatible = "regulator-fixed";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_reg_usb_otg1>;
+               regulator-name = "usb_otg_vbus";
+               regulator-min-microvolt = <5000000>;
+               regulator-max-microvolt = <5000000>;
+               gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
+               enable-active-high;
+       };
+
        reg_usdhc2_vmmc: regulator-usdhc2 {
                compatible = "regulator-fixed";
                regulator-name = "VSD_3V3";
@@ -102,7 +113,6 @@
                compatible = "wlf,wm8962";
                reg = <0x1a>;
                clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
-               clock-names = "xclk";
                DCVDD-supply = <&reg_audio>;
                DBVDD-supply = <&reg_audio>;
                AVDD-supply = <&reg_audio>;
@@ -170,6 +180,24 @@
        status = "okay";
 };
 
+&usbotg1 {
+       vbus-supply = <&reg_usbotg1>;
+       disable-over-current;
+       dr_mode="otg";
+       status = "okay";
+};
+
+&usbotg2 {
+       pinctrl-names = "default";
+       disable-over-current;
+       dr_mode="host";
+       status = "okay";
+};
+
+&usbphynop2 {
+       reset-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>;
+};
+
 &usdhc2 {
        pinctrl-names = "default", "state_100mhz", "state_200mhz";
        pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
@@ -216,6 +244,12 @@
                >;
        };
 
+       pinctrl_reg_usb_otg1: usbotg1grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29     0x19
+               >;
+       };
+
        pinctrl_sai3: sai3grp {
                fsl,pins = <
                        MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6

diff --git a/arch/arm/dts/imx8mm-beacon-som.dtsi b/arch/arm/dts/imx8mm-beacon-som.dtsi
index d897913537ca1f940b4cb4df7c0e5e62fe0fb758..cf07987ccc10b68dd95a1fed4fe01a32b7131e68 100644 (file)
--- a/arch/arm/dts/imx8mm-beacon-som.dtsi
+++ b/arch/arm/dts/imx8mm-beacon-som.dtsi
@@ -91,7 +91,7 @@
                #size-cells = <1>;
                compatible = "jedec,spi-nor";
                spi-max-frequency = <80000000>;
-               spi-tx-bus-width = <4>;
+               spi-tx-bus-width = <1>;
                spi-rx-bus-width = <4>;
        };
 };
@@ -256,12 +256,13 @@
 &usdhc1 {
        #address-cells = <1>;
        #size-cells = <0>;
-       pinctrl-names = "default";
+       pinctrl-names = "default", "state_100mhz", "state_200mhz";
        pinctrl-0 = <&pinctrl_usdhc1>;
+       pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+       pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
        bus-width = <4>;
        non-removable;
        cap-power-off-card;
-       pm-ignore-notify;
        keep-power-in-suspend;
        mmc-pwrseq = <&usdhc1_pwrseq>;
        status = "okay";