armv8/layerscape: Update MMU table with execute-never bits

For most device addresses excution shouldn't be allowed. Revise
the MMU table to enforce execute-never bits. OCRAM, DDR and IFC
are allowed for excution.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reported-by: Zhichun Hua <zhichun.hua@freescale.com>

diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 1ece6a2c12268714fee08d4a70d932b165ce41b8..53bac3b4495a597497420a7bc91ae8cbd29a7480 100644 (file)
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -13,13 +13,13 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #ifndef CONFIG_SYS_DCACHE_OFF
 inline void set_pgtable_section(u64 *page_table, u64 index, u64 section,
-                        u64 memory_type, u64 share)
+                        u64 memory_type, u64 attribute)
 {
        u64 value;
 
        value = section | PMD_TYPE_SECT | PMD_SECT_AF;
        value |= PMD_ATTRINDX(memory_type);
-       value |= share;
+       value |= attribute;
        page_table[index] = value;
 }
 

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index c6e00b8c2082b517aa34e32ccc76f605752124f9..571ee7b70d957331c0201da06aa2cce04979fa0b 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -76,7 +76,7 @@ static int set_block_entry(const struct sys_mmu_table *list,
                                    index,
                                    block_addr,
                                    list->memory_type,
-                                   list->share);
+                                   list->attribute);
                block_addr += block_size;
                index++;
        }

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 48b6cd4f4f0fcb66c5dff9e2db4aa1a424f40982..727fd24937f73520a6d7efd6d895ee84138838d7 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -103,7 +103,7 @@ struct sys_mmu_table {
        u64 phys_addr;
        u64 size;
        u64 memory_type;
-       u64 share;
+       u64 attribute;
 };
 
 struct table_info {
@@ -115,7 +115,8 @@ struct table_info {
 static const struct sys_mmu_table early_mmu_table[] = {
 #ifdef CONFIG_FSL_LSCH3
        { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
-         CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
        { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
          CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
        /* For IFC Region #1, only the first 4MB is cache-enabled */
@@ -130,16 +131,19 @@ static const struct sys_mmu_table early_mmu_table[] = {
        { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
          CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
        { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
-         CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
        { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
          CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
 #elif defined(CONFIG_FSL_LSCH2)
        { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
-         CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
        { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
          CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
        { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
-         CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
        { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
          CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
        { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
@@ -152,72 +156,93 @@ static const struct sys_mmu_table early_mmu_table[] = {
 static const struct sys_mmu_table final_mmu_table[] = {
 #ifdef CONFIG_FSL_LSCH3
        { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
-         CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
        { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
          CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
        { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
          CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
        { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
-         CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
        { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
          CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
        { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
-         CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
        { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
-         CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
        { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
-         CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
        /* For QBMAN portal, only the first 64MB is cache-enabled */
        { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
-         CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
        { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
          CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
          CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
-         MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
        { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
-         CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
        { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
-         CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
        { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
-         CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
 #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
        { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
-         CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
 #endif
        { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
-         CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
        { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
-         CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
        { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
-         CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
        { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
          CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
 #elif defined(CONFIG_FSL_LSCH2)
        { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
-         CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
        { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
-         CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
        { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
          CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
        { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
-         CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
        { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
-         CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
        { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
          CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
        { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
          CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
          PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
        { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
-         CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
        { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
          CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
        { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
-         CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
        { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
-         CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
        { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
-         CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
+         PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
        { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
          CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE },
 #endif

diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index d8d9af45db4f186a528bf56e90ffda51f05775f4..2e2a3a8226d9a6c37fd3336f907e43a26e5d39aa 100644 (file)
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -119,7 +119,7 @@
 
 void set_pgtable_section(u64 *page_table, u64 index,
                         u64 section, u64 memory_type,
-                        u64 share);
+                        u64 attribute);
 void set_pgtable_table(u64 *page_table, u64 index,
                       u64 *table_addr);