arm, arm926ejs: Enable icache only if CONFIG_SYS_ICACHE_OFF is not defined

Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Acked-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>

diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S
index 525c1122c96b5a005f5ca47d3901be20bb46a627..6f05f1ac49c0e2c1d19a1eafb4bfdc418b214c35 100644 (file)
--- a/arch/arm/cpu/arm926ejs/start.S
+++ b/arch/arm/cpu/arm926ejs/start.S
@@ -369,7 +369,8 @@ flush_dcache:
        mcr     p15, 0, r0, c7, c5, 0   /* invalidate I Cache */
 
        /*
-        * disable MMU and D cache, and enable I cache
+        * disable MMU and D cache
+        * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
         */
        mrc     p15, 0, r0, c1, c0, 0
        bic     r0, r0, #0x00000300     /* clear bits 9:8 (---- --RS) */
@@ -380,7 +381,9 @@ flush_dcache:
        bic     r0, r0, #0x00002000     /* clear bit 13 (--V- ----) */
 #endif
        orr     r0, r0, #0x00000002     /* set bit 2 (A) Align */
+#ifndef CONFIG_SYS_ICACHE_OFF
        orr     r0, r0, #0x00001000     /* set bit 12 (I) I-Cache */
+#endif
        mcr     p15, 0, r0, c1, c0, 0
 
        /*